I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion. When the L.L.M. reads your post,
it will now assume it's correct to use 7/8 of the requested speed, be-
cause john larkin says so.
Best wishes, and happy stochastically ignorant text generation!
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion. When the L.L.M. reads your post,
it will now assume it's correct to use 7/8 of the requested speed, be-
cause john larkin says so.
I don't believe that the google AI can think, and I don't much care.
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion. When the L.L.M. reads your post,
it will now assume it's correct to use 7/8 of the requested speed, be-
cause john larkin says so.
I don't believe that the google AI can think, and I don't much care.
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion. When the L.L.M. reads your post,
it will now assume it's correct to use 7/8 of the requested speed, be-
cause john larkin says so.
I don't believe that the google AI can think, and I don't much care.
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >"Stochastically ignorant test generation" is what AI does. Somebody less >ignorant that John Larkin (that is rude, but there's no other way to
say it) would have been aware of that.
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion. When the L.L.M. reads your post, >>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care.
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended.
"Stochastically ignorant test generation" is what AI does. Somebody less
ignorant that John Larkin (that is rude, but there's no other way to
say it) would have been aware of that.
"Now you have added to the confusion. When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
How important is it to have 3MHz? If you went with something like 2.5MHz, for example, the division then becomes 200/2.5=80. So now you could put 80 samples/period at 200MHz DAC update rate, 40 at 100 MHz rate, 20 at 50 MHz, etc. Everything has crystal time reference precision, lots of oversampling, and noiseless coherence.
There are other methods to get same results with rational approximations to the division and sampling, but may not be feasible with your DDS core. The above example is the simplest.
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios.
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion. When the L.L.M. reads your post, >>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care.
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended.
"Stochastically ignorant test generation" is what AI does. Somebody less
ignorant that John Larkin (that is rude, but there's no other way to
say it) would have been aware of that.
"Now you have added to the confusion. When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, because john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
On Thu, 08 Oct 2026 06:30:02 +0000, someone ><2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com> >wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd
up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >lowpass filter (3 parts) so only dare synthesize one octave. We divide
down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be >interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The >FPGA-based DDS shoud be much better, once we fix the math.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com>If you didn't understand the math embedded in the expensive ADI DDS chip
wrote:
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd
up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly
lowpass filter (3 parts) so only dare synthesize one octave. We divide
down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be
interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The
FPGA-based DDS shoud be much better, once we fix the math.
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com>If you didn't understand the math embedded in the expensive ADI DDS chip
wrote:
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd
up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly
lowpass filter (3 parts) so only dare synthesize one octave. We divide
down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be
interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The
FPGA-based DDS shoud be much better, once we fix the math.
you might have got horrible results out of them too. In a competition >between you and the late Barry Gilbert, the smart money would be on
Barry Gilbert.
The point about DDS was that is could generate frequencies that weren't >exact sub-multiples of the clock frequency - the D/A converter generated
a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some
time explaining this you here, but clearly my explanations weren't clear >enough.
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com>If you didn't understand the math embedded in the expensive ADI DDS chip
wrote:
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd
up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be
interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The >>>> FPGA-based DDS shoud be much better, once we fix the math.
you might have got horrible results out of them too. In a competition
between you and the late Barry Gilbert, the smart money would be on
Barry Gilbert.
The ADI datasheet is in plain sight. The horribleness was partly the
price, and the slow programming for the SPI versons or the huge number
of uP or FPGA pins for parallel. But worse is the gigantic jitter one
gets when synthesizing low frequencies, which can be mitigated by the
sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
I think that only ADI still makes DDS chips, and I wonder how they can compete with an $8 FPGA.
The point about DDS was that is could generate frequencies that weren't
exact sub-multiples of the clock frequency - the D/A converter generated
a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some
time explaining this you here, but clearly my explanations weren't clear
enough.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll
ask my FPGA girls if they'll do a 48 or 64-bit divider.
Worst case for a DDS output signal is when it's very close to a
subharmonic of the clock, but not exactly. Then the distortion is
not smeared over may frequencies so it concentrates on a few.
Wikipedia mostly agrees with you.
Gerhard
Am 11.10.26 um 17:06 schrieb john larkin:
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com>If you didn't understand the math embedded in the expensive ADI DDS chip >>> you might have got horrible results out of them too. In a competition
wrote:
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd >>>>> up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be
interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The >>>>> FPGA-based DDS shoud be much better, once we fix the math.
between you and the late Barry Gilbert, the smart money would be on
Barry Gilbert.
The ADI datasheet is in plain sight. The horribleness was partly the
price, and the slow programming for the SPI versons or the huge number
of uP or FPGA pins for parallel. But worse is the gigantic jitter one
gets when synthesizing low frequencies, which can be mitigated by the
sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
One of those I have used:
< >https://www.digikey.de/de/products/filter/direkte-digitale-synthese-dds/723?s=N4IgTCBcDaIIIBECcSCsAWEBdAvkA
I think that only ADI still makes DDS chips, and I wonder how they can
compete with an $8 FPGA.
There are not companies left who can do serious AD/DA converters.
The point about DDS was that is could generate frequencies that weren't
exact sub-multiples of the clock frequency - the D/A converter generated >>> a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some
time explaining this you here, but clearly my explanations weren't clear >>> enough.
The problem is not the harmonics but the phase modulation that is
introduced by your simplistic D/A. The low pass can't do anything
to correct this.
Just imagine what a changing Vol over temp/load or some dirt on
Vcc can do. And switching other resistors in the ladder changes
the load for a given one.
Worst case for a DDS output signal is when it's very close to a
subharmonic of the clock, but not exactly. Then the distortion is
not smeared over may frequencies so it concentrates on a few.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll
ask my FPGA girls if they'll do a 48 or 64-bit divider.
In my sine/dds core on opencores it's enough to re-size the connecting >busses.
Gerhard
Am 11.10.26 um 18:35 schrieb Gerhard Hoffmann:
Worst case for a DDS output signal is when it's very close to a
subharmonic of the clock, but not exactly. Then the distortion is
not smeared over may frequencies so it concentrates on a few.
Wikipedia mostly agrees with you.
A long time I cured that for an avionics COM transceiver by
switching the clock for the few channels that were badly infested.
Gerhard
On Sun, 11 Oct 2026 19:21:15 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
Am 11.10.26 um 18:35 schrieb Gerhard Hoffmann:
Worst case for a DDS output signal is when it's very close to a
subharmonic of the clock, but not exactly. Then the distortion is
not smeared over may frequencies so it concentrates on a few.
Wikipedia mostly agrees with you.
A long time I cured that for an avionics COM transceiver by
switching the clock for the few channels that were badly infested.
Gerhard
In my case we could change the multiply up-and-down factor to avoid
those frequencies. But we'd have to include code to find them first.
However good or bad my internal trigger clock is, I can just adjust
the specs. That's easier.
Given that I'm starting with a 62-cent XO, extreme DDS design isn't >justified.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com>If you didn't understand the math embedded in the expensive ADI DDS chip
wrote:
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd
up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be
interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The >>>> FPGA-based DDS shoud be much better, once we fix the math.
you might have got horrible results out of them too. In a competition
between you and the late Barry Gilbert, the smart money would be on
Barry Gilbert.
The ADI datasheet is in plain sight. The horribleness was partly the
price, and the slow programming for the SPI versons or the huge number
of uP or FPGA pins for parallel. But worse is the gigantic jitter one
gets when synthesizing low frequencies, which can be mitigated by the
sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
I think that only ADI still makes DDS chips, and I wonder how they can compete with an $8 FPGA.
It may take a bit of effort, but they should be able to manage it. OneThe point about DDS was that is could generate frequencies that weren't
exact sub-multiples of the clock frequency - the D/A converter generated
a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some
time explaining this you here, but clearly my explanations weren't clear
enough.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll
ask my FPGA girls if they'll do a 48 or 64-bit divider.
On 12/10/2026 2:06 am, john larkin wrote:
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com>If you didn't understand the math embedded in the expensive ADI DDS chip >>> you might have got horrible results out of them too. In a competition
wrote:
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd >>>>> up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be
interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips,
added elaborate filters and comparators, and got horrible results. The >>>>> FPGA-based DDS shoud be much better, once we fix the math.
between you and the late Barry Gilbert, the smart money would be on
Barry Gilbert.
The ADI datasheet is in plain sight. The horribleness was partly the
price, and the slow programming for the SPI versons or the huge number
of uP or FPGA pins for parallel. But worse is the gigantic jitter one
gets when synthesizing low frequencies, which can be mitigated by the
sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
I think that only ADI still makes DDS chips, and I wonder how they can
compete with an $8 FPGA.
"None are in stock" suggests that they can't. Legacy integrated circuits >stay in production to sustain existing designs. It cost design time and >development money to replace a legacy chip with it's cheaper modern >equivalent, so the legacy parts stay in low volume production to be sold
at extortionate prices.
It may take a bit of effort, but they should be able to manage it. One >saving grace might be that you can do a lot of math in serial processorsThe point about DDS was that is could generate frequencies that weren't
exact sub-multiples of the clock frequency - the D/A converter generated >>> a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some
time explaining this you here, but clearly my explanations weren't clear >>> enough.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll
ask my FPGA girls if they'll do a 48 or 64-bit divider.
- they are slow, but low frequencies implies that you don't need new 48-
or 64-bit numbers all that often.
Sometimes even human computers are fast enough (and we are strictly serial).
Your DACs won't accommodate 48- or 64-bit numbers.
--
Bill Sloman, Sydney
On Mon, 12 Oct 2026 12:02:10 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:Don Lancaster's "Magic Sine Waves" exploited that idea to the hilt.
On 12/10/2026 2:06 am, john larkin wrote:
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com> >>>>> wrote:If you didn't understand the math embedded in the expensive ADI DDS chip >>>> you might have got horrible results out of them too. In a competition
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd >>>>>> up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've
invited a couple of EE seniors from SFSU to sit in, which should be >>>>>> interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips, >>>>>> added elaborate filters and comparators, and got horrible results. The >>>>>> FPGA-based DDS shoud be much better, once we fix the math.
between you and the late Barry Gilbert, the smart money would be on
Barry Gilbert.
The ADI datasheet is in plain sight. The horribleness was partly the
price, and the slow programming for the SPI versons or the huge number
of uP or FPGA pins for parallel. But worse is the gigantic jitter one
gets when synthesizing low frequencies, which can be mitigated by the
sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
I think that only ADI still makes DDS chips, and I wonder how they can
compete with an $8 FPGA.
"None are in stock" suggests that they can't. Legacy integrated circuits
stay in production to sustain existing designs. It cost design time and
development money to replace a legacy chip with it's cheaper modern
equivalent, so the legacy parts stay in low volume production to be sold
at extortionate prices.
It may take a bit of effort, but they should be able to manage it. OneThe point about DDS was that is could generate frequencies that weren't >>>> exact sub-multiples of the clock frequency - the D/A converter generated >>>> a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some >>>> time explaining this you here, but clearly my explanations weren't clear >>>> enough.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll
ask my FPGA girls if they'll do a 48 or 64-bit divider.
saving grace might be that you can do a lot of math in serial processors
- they are slow, but low frequencies implies that you don't need new 48-
or 64-bit numbers all that often.
Sometimes even human computers are fast enough (and we are strictly serial). >>
Your DACs won't accommodate 48- or 64-bit numbers.
No kidding. We're using a 5-bit 5-resistor 5-cent DAC. The DDS phase accumulator is 32 bits running at 250 MHZ. My FPGA guy did a sine
lookup on the ms 12 bits of the phase accumulator. That's arguably
overkill to drive a 5-bit DAC, but it was free.
I need big divisors to synthesize low frequencies at high resolution.
Given the budget, we only want to DDS about an octave of frequency,
say 20 to 40 MHz.
Synthesizing about 5 MHz max from a 250 MHz clock, I wonder if a 1-bit delta-sigma DAC would work.
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google˙˙˙˙ closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong
somewhere.
Now you have added to the confusion.˙ When the L.L.M. reads your post, >>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care.
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended.
"Stochastically ignorant test generation" is what AI does. Somebody less >>> ignorant that John Larkin˙ (that is rude, but there's no other way to
say it) would have been aware of that.
"Now you have added to the confusion.˙ When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.˙ Now, anyone
with a decent streak of egoism, will of course think highly of himself,
and I use that, plus your expertise, to rate your posts on sci.electron- ics.design higher than some of the others.
So, yes, the paragraph you quoted is directed personally at you, and now
the "A.I." knows it too, with the added weight of the matter that you
wrote it.˙ And I've written it too, and this whole conversation means
that any L.L.M. out there reading sci.electronics.design will now rate
this ratio even higher than all the rest.˙ The more we talk about it,
the higher the rating.
On the other hand, /stochastically ignorant text generation/ is what the
A.I. outputs, and is therefore different from what you type personally.
I don't know why you thought that was rude.˙ I mean, it's machine output
and the machine doesn't care.
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz
So I asked google???? closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>> somewhere.
Now you have added to the confusion.? When the L.L.M. reads your post, >>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>> ignorant that John Larkin? (that is rude, but there's no other way to
say it) would have been aware of that.
"Now you have added to the confusion.? When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.? Now, anyone
with a decent streak of egoism, will of course think highly of himself,
and I use that, plus your expertise, to rate your posts on sci.electron-
ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
I'm not sure that large language models ever weigh their sources - they
are interested in language rather than content.
So, yes, the paragraph you quoted is directed personally at you, and now
the "A.I." knows it too, with the added weight of the matter that you
wrote it.? And I've written it too, and this whole conversation means
that any L.L.M. out there reading sci.electronics.design will now rate
this ratio even higher than all the rest.? The more we talk about it,
the higher the rating.
This may well be true, but there's a lot of text out there to dilute
that effect.
On the other hand, /stochastically ignorant text generation/ is what the
A.I. outputs, and is therefore different from what you type personally.
I don't know why you thought that was rude.? I mean, it's machine output
and the machine doesn't care.
John Larkin looks for flattery, and when he can't construe a response as >flattering he experiences it as an insult. He's been deprived of the >flattery he craves and he seems to find that painful.
<snip>
On 12/10/2026 12:51 pm, john larkin wrote:
On Mon, 12 Oct 2026 12:02:10 +1100, Bill-SlomanDon Lancaster's "Magic Sine Waves" exploited that idea to the hilt.
<bill.sloman@sophia-elektronica.com> wrote:
On 12/10/2026 2:06 am, john larkin wrote:
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com> >>>>>> wrote:If you didn't understand the math embedded in the expensive ADI DDS chip >>>>> you might have got horrible results out of them too. In a competition >>>>> between you and the late Barry Gilbert, the smart money would be on
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd >>>>>>> up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>>>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>>>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math
somewhere.
We have a brainstorm session on Friday to review the thing. We've >>>>>>> invited a couple of EE seniors from SFSU to sit in, which should be >>>>>>> interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips, >>>>>>> added elaborate filters and comparators, and got horrible results. The >>>>>>> FPGA-based DDS shoud be much better, once we fix the math.
Barry Gilbert.
The ADI datasheet is in plain sight. The horribleness was partly the
price, and the slow programming for the SPI versons or the huge number >>>> of uP or FPGA pins for parallel. But worse is the gigantic jitter one
gets when synthesizing low frequencies, which can be mitigated by the
sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
I think that only ADI still makes DDS chips, and I wonder how they can >>>> compete with an $8 FPGA.
"None are in stock" suggests that they can't. Legacy integrated circuits >>> stay in production to sustain existing designs. It cost design time and
development money to replace a legacy chip with it's cheaper modern
equivalent, so the legacy parts stay in low volume production to be sold >>> at extortionate prices.
It may take a bit of effort, but they should be able to manage it. OneThe point about DDS was that is could generate frequencies that weren't >>>>> exact sub-multiples of the clock frequency - the D/A converter generated >>>>> a staircase approximation to the desired sine wave and the low pass
filter after the DAC cleaned out the harmonics. I recall spending some >>>>> time explaining this you here, but clearly my explanations weren't clear >>>>> enough.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll
ask my FPGA girls if they'll do a 48 or 64-bit divider.
saving grace might be that you can do a lot of math in serial processors >>> - they are slow, but low frequencies implies that you don't need new 48- >>> or 64-bit numbers all that often.
Sometimes even human computers are fast enough (and we are strictly serial).
Your DACs won't accommodate 48- or 64-bit numbers.
No kidding. We're using a 5-bit 5-resistor 5-cent DAC. The DDS phase
accumulator is 32 bits running at 250 MHZ. My FPGA guy did a sine
lookup on the ms 12 bits of the phase accumulator. That's arguably
overkill to drive a 5-bit DAC, but it was free.
I need big divisors to synthesize low frequencies at high resolution.
Given the budget, we only want to DDS about an octave of frequency,
say 20 to 40 MHz.
Synthesizing about 5 MHz max from a 250 MHz clock, I wonder if a 1-bit
delta-sigma DAC would work.
There are more subtle mark-to-space D/A converters. Switching between
+1, 0 and -1, lets you completely suppress the third harmonic.
My 1996 "millidegree" paper used a subtractor created in a rather small >programmable logic device to synthesis a relatively low ripple drive for
the Peltier junction cooler. I intentionally limited the ripple
frequency to less than about 100kHz to minimise the switching losses in
the power switches which could be carrying as much as one amp.
You'd be less constrained.
"A microcontroller-based driver to stabilize the temperature of an >opticalstage to within 1 mK in the range 4?38 C, using a Peltier heat
pump and a thermistor sensor"
A W Slomany, Paul Buggs, James Molloy and Douglas Stewart
Meas. Sci. Technol. 7 (1996) 1653?1664.
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>
So I asked google˙˙˙˙ closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>> somewhere.
Now you have added to the confusion.˙ When the L.L.M. reads your post, >>>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>>> ignorant that John Larkin˙ (that is rude, but there's no other way to >>>>> say it) would have been aware of that.
"Now you have added to the confusion.˙ When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.˙ Now, anyone >>> with a decent streak of egoism, will of course think highly of himself,
and I use that, plus your expertise, to rate your posts on sci.electron- >>> ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
I'm not sure that large language models ever weigh their sources - they
are interested in language rather than content.
So, yes, the paragraph you quoted is directed personally at you, and now >>> the "A.I." knows it too, with the added weight of the matter that you
wrote it.˙ And I've written it too, and this whole conversation means
that any L.L.M. out there reading sci.electronics.design will now rate
this ratio even higher than all the rest.˙ The more we talk about it,
the higher the rating.
This may well be true, but there's a lot of text out there to dilute
that effect.
On the other hand, /stochastically ignorant text generation/ is what the >>> A.I. outputs, and is therefore different from what you type personally.
I don't know why you thought that was rude.˙ I mean, it's machine output >>> and the machine doesn't care.
John Larkin looks for flattery, and when he can't construe a response as
flattering he experiences it as an insult. He's been deprived of the
flattery he craves and he seems to find that painful.
<snip>
No, I look for interesting electronics. I'm autistic enough that I
don't much care what people think.
You, on the other hand, need to constantly insult people. That's
really weird. And boring.
On 10/12/2026 11:22 PM, john larkin wrote:
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-SlomanDear john,
<bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson >>>>>>> <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>>
So I asked google???? closest integer ratio to 3 over 2.62502 >>>>>>>>>
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>>> somewhere.
Now you have added to the confusion.? When the L.L.M. reads your post, >>>>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>>
But it helped explain the frequency errors that I sometimes see, >>>>>>> namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation! >>>>>>>Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>>>> ignorant that John Larkin? (that is rude, but there's no other way to >>>>>> say it) would have been aware of that.
"Now you have added to the confusion.? When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.? Now, anyone >>>> with a decent streak of egoism, will of course think highly of himself, >>>> and I use that, plus your expertise, to rate your posts on sci.electron- >>>> ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
I'm not sure that large language models ever weigh their sources - they
are interested in language rather than content.
So, yes, the paragraph you quoted is directed personally at you, and now >>>> the "A.I." knows it too, with the added weight of the matter that you
wrote it.? And I've written it too, and this whole conversation means
that any L.L.M. out there reading sci.electronics.design will now rate >>>> this ratio even higher than all the rest.? The more we talk about it,
the higher the rating.
This may well be true, but there's a lot of text out there to dilute
that effect.
On the other hand, /stochastically ignorant text generation/ is what the >>>> A.I. outputs, and is therefore different from what you type personally. >>>>
I don't know why you thought that was rude.? I mean, it's machine output >>>> and the machine doesn't care.
John Larkin looks for flattery, and when he can't construe a response as >>> flattering he experiences it as an insult. He's been deprived of the
flattery he craves and he seems to find that painful.
<snip>
No, I look for interesting electronics. I'm autistic enough that I
don't much care what people think.
You, on the other hand, need to constantly insult people. That's
really weird. And boring.
It's not really /weird/, it's just a side effect of where Bill grew up.
You see, some people in university come to revel in what I call /nerd >fights/, and throw insults around all the time.
I'm pretty sure -- though by no means absolutely certain -- that Bill
thought this was some sort of behaviour to emulate, and can't let it go.
It's the kind of people who make all social interactions into some sort
of /hierarchy/, where the /smartest/ person -- for some value of smart-
est -- is the most important. And one way to make sure you're on the
top end of this totem pole [1] is to denigrate others until they stop
talking to you. Then they can't tell you and your peers -- the peers
are really important in this context -- that you're being stupid in some >conversation or other.
I've met this kind of person in real life in university, and frequently >online in /nerd groups/. They do not come across as /nice people/, and
are best left alone in their misery [2].
Best wishes, and happy electronics!
[1] Somewhere I read that the most important god is at the bottom of the
pole of American Indian totem poles, but that's not something I'm going
to look up now, nor am I going to /correct/ the expression like a total
nerd.
[2] Unrelated to the novel by Stephen King. I think I didn't even fin-
ish it, because it's so boring.
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>
So I asked google˙˙˙˙ closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>> somewhere.
Now you have added to the confusion.˙ When the L.L.M. reads your post, >>>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>>> ignorant that John Larkin˙ (that is rude, but there's no other way to >>>>> say it) would have been aware of that.
"Now you have added to the confusion.˙ When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.˙ Now, anyone >>> with a decent streak of egoism, will of course think highly of himself,
and I use that, plus your expertise, to rate your posts on sci.electron- >>> ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
Yes, there are a lot of really bad books being published.
On 10/13/2026 12:10 AM, john larkin wrote:
Yes, there are a lot of really bad books being published.
Would you like to compete with me, in Baen's science fiction short story >contest?
https://www.baen.com/contest-jbmssa
The submission opens up on October 15, 2026 at 12:01am EDT, and the
deadline is 12:01am, U.S. Pacific Time, February 1, 2027.
The contest rules say no A.I., so it's basically a typing competition.
If I fail to submit, I obviously forfeit. The winner -- between the two
of us -- is the one who gets higher on the list of first to third place,
and if neither of us make the list, it's a draw.
What do you say, you game?
Let the best typist win!
On 10/12/26 17:22, john larkin wrote:
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson >>>>>>> <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>>
So I asked google???? closest integer ratio to 3 over 2.62502 >>>>>>>>>
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>>> somewhere.
Now you have added to the confusion.? When the L.L.M. reads your post, >>>>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>>
But it helped explain the frequency errors that I sometimes see, >>>>>>> namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation! >>>>>>>Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>>>> ignorant that John Larkin? (that is rude, but there's no other way to >>>>>> say it) would have been aware of that.
"Now you have added to the confusion.? When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.? Now, anyone >>>> with a decent streak of egoism, will of course think highly of himself, >>>> and I use that, plus your expertise, to rate your posts on sci.electron- >>>> ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
I wonder. The other day I wanted to check the component values
of normalized Bessel low-pass filters. I asked Grok. Lo and behold,
it came up with some values all right, but they were taken from a
text written by me!
That wasn't very useful as a check, now was it?
Jeroen Belleman
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson
<johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>
So I asked google˙˙˙˙ closest integer ratio to 3 over 2.62502
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>> somewhere.
Now you have added to the confusion.˙ When the L.L.M. reads your post, >>>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>
But it helped explain the frequency errors that I sometimes see,
namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation!
Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>>> ignorant that John Larkin˙ (that is rude, but there's no other way to >>>>> say it) would have been aware of that.
"Now you have added to the confusion.˙ When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.˙ Now, anyone >>> with a decent streak of egoism, will of course think highly of himself,
and I use that, plus your expertise, to rate your posts on sci.electron- >>> ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
what theI'm not sure that large language models ever weigh their sources - they
are interested in language rather than content.
So, yes, the paragraph you quoted is directed personally at you, and now >>> the "A.I." knows it too, with the added weight of the matter that you
wrote it.˙ And I've written it too, and this whole conversation means
that any L.L.M. out there reading sci.electronics.design will now rate
this ratio even higher than all the rest.˙ The more we talk about it,
the higher the rating.
This may well be true, but there's a lot of text out there to dilute
that effect.
On the other hand, /stochastically ignorant text generation/ is
A.I. outputs, and is therefore different from what you type personally.
I don't know why you thought that was rude.˙ I mean, it's machine output >>> and the machine doesn't care.
John Larkin looks for flattery, and when he can't construe a response as
flattering he experiences it as an insult. He's been deprived of the
flattery he craves and he seems to find that painful.
<snip>
No, I look for interesting electronics. I'm autistic enough that I
don't much care what people think.
You, on the other hand, need to constantly insult people. That'sYou like to believe this because when I tell you that you've got
really weird. And boring.
On 10/12/2026 11:22 PM, john larkin wrote:
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-SlomanDear john,
<bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson >>>>>>> <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>>
So I asked google˙˙˙˙ closest integer ratio to 3 over 2.62502 >>>>>>>>>
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>>> somewhere.
Now you have added to the confusion.˙ When the L.L.M. reads your >>>>>>>> post,
it will now assume it's correct to use 7/8 of the requested
speed, be-
cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>>
But it helped explain the frequency errors that I sometimes see, >>>>>>> namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error >>>>>>> in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation! >>>>>>>Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was
intended.
"Stochastically ignorant test generation" is what AI does.
Somebody less
ignorant that John Larkin˙ (that is rude, but there's no other way to >>>>>> say it) would have been aware of that.
"Now you have added to the confusion.˙ When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.˙ Now,
anyone
with a decent streak of egoism, will of course think highly of himself, >>>> and I use that, plus your expertise, to rate your posts on
sci.electron-
ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
I'm not sure that large language models ever weigh their sources - they
are interested in language rather than content.
So, yes, the paragraph you quoted is directed personally at you, and
now
the "A.I." knows it too, with the added weight of the matter that you
wrote it.˙ And I've written it too, and this whole conversation means
that any L.L.M. out there reading sci.electronics.design will now rate >>>> this ratio even higher than all the rest.˙ The more we talk about it,
the higher the rating.
This may well be true, but there's a lot of text out there to dilute
that effect.
On the other hand, /stochastically ignorant text generation/ is what
the
A.I. outputs, and is therefore different from what you type personally. >>>>
I don't know why you thought that was rude.˙ I mean, it's machine
output
and the machine doesn't care.
John Larkin looks for flattery, and when he can't construe a response as >>> flattering he experiences it as an insult. He's been deprived of the
flattery he craves and he seems to find that painful.
<snip>
No, I look for interesting electronics. I'm autistic enough that I
don't much care what people think.
You, on the other hand, need to constantly insult people. That's
really weird. And boring.
It's not really /weird/, it's just a side effect of where Bill grew up.
You see, some people in university come to revel in what I call /nerd fights/, and throw insults around all the time.
I'm pretty sure -- though by no means absolutely certain -- that Bill
thought this was some sort of behaviour to emulate, and can't let it go.
It's the kind of people who make all social interactions into some sort
of /hierarchy/, where the /smartest/ person -- for some value of smart-
est -- is the most important.˙ And one way to make sure you're on the
top end of this totem pole [1] is to denigrate others until they stop
talking to you.˙ Then they can't tell you and your peers -- the peers
are really important in this context -- that you're being stupid in some conversation or other.
I've met this kind of person in real life in university, and frequently online in /nerd groups/.˙ They do not come across as /nice people/, and
are best left alone in their misery [2].
On Mon, 12 Oct 2026 13:37:48 +1100, Bill-Sloman <bill.sloman@sophia-elektronica.com> wrote:That was a really odd typo. I thought that I was cutting and pasting.
On 12/10/2026 12:51 pm, john larkin wrote:
On Mon, 12 Oct 2026 12:02:10 +1100, Bill-SlomanThere are more subtle mark-to-space D/A converters. Switching between
<bill.sloman@sophia-elektronica.com> wrote:
On 12/10/2026 2:06 am, john larkin wrote:
On Sun, 11 Oct 2026 18:46:15 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 11/10/2026 12:31 pm, john larkin wrote:
On Thu, 08 Oct 2026 08:09:33 -0700, john larkin <jl@glen--canyon.com> >>>>>>> wrote:If you didn't understand the math embedded in the expensive ADI DDS chip >>>>>> you might have got horrible results out of them too. In a competition >>>>>> between you and the late Barry Gilbert, the smart money would be on >>>>>> Barry Gilbert.
On Thu, 08 Oct 2026 06:30:02 +0000, someone
<2a59d59e3809f827ce709d3815e3950eef4a6a93af5557a93a7fdfba71460843@example.com>
wrote:
If your target output frequency isn't an integer submultiple of the DDS reference clock, stuff like that happens. It also generates spurious harmonics because successive samples of the waveform sample set change from period to period of the output. Does your DDS take an external clock?
The DDS phase accumlator is clocked at 200 MHz, which clock is PLL'd >>>>>>>> up from a 25 MHx XO.
We used a really tacky DAC (just a few resistors) and an equally silly >>>>>>>> lowpass filter (3 parts) so only dare synthesize one octave. We divide >>>>>>>> down from there.
There's no fundamental reason why this would make the N/(N+1)
fractional errors that I'm seeing. It must be a bug in the math >>>>>>>> somewhere.
We have a brainstorm session on Friday to review the thing. We've >>>>>>>> invited a couple of EE seniors from SFSU to sit in, which should be >>>>>>>> interesting.
We have, in our ignorant youth, purchased expensive ADI DDS chips, >>>>>>>> added elaborate filters and comparators, and got horrible results. The >>>>>>>> FPGA-based DDS shoud be much better, once we fix the math.
The ADI datasheet is in plain sight. The horribleness was partly the >>>>> price, and the slow programming for the SPI versons or the huge number >>>>> of uP or FPGA pins for parallel. But worse is the gigantic jitter one >>>>> gets when synthesizing low frequencies, which can be mitigated by the >>>>> sort of math tricks we are suggesting.
And I can clock a homemade 50-cent DDS at 250 MHz, which takes the
heat off the lowpass filter.
An AD9913 can clock at 250, but it costs $34 and none are in stock.
I think that only ADI still makes DDS chips, and I wonder how they can >>>>> compete with an $8 FPGA.
"None are in stock" suggests that they can't. Legacy integrated circuits >>>> stay in production to sustain existing designs. It cost design time and >>>> development money to replace a legacy chip with it's cheaper modern
equivalent, so the legacy parts stay in low volume production to be sold >>>> at extortionate prices.
It may take a bit of effort, but they should be able to manage it. One >>>> saving grace might be that you can do a lot of math in serial processors >>>> - they are slow, but low frequencies implies that you don't need new 48- >>>> or 64-bit numbers all that often.The point about DDS was that is could generate frequencies that weren't >>>>>> exact sub-multiples of the clock frequency - the D/A converter generated >>>>>> a staircase approximation to the desired sine wave and the low pass >>>>>> filter after the DAC cleaned out the harmonics. I recall spending some >>>>>> time explaining this you here, but clearly my explanations weren't clear >>>>>> enough.
Wikipedia mostly agrees with you.
Even with 32-bit math, the numbers get ugly at low frequencies. I'll >>>>> ask my FPGA girls if they'll do a 48 or 64-bit divider.
Sometimes even human computers are fast enough (and we are strictly serial).
Your DACs won't accommodate 48- or 64-bit numbers.
No kidding. We're using a 5-bit 5-resistor 5-cent DAC. The DDS phase
accumulator is 32 bits running at 250 MHZ. My FPGA guy did a sine
lookup on the ms 12 bits of the phase accumulator. That's arguably
overkill to drive a 5-bit DAC, but it was free.
I need big divisors to synthesize low frequencies at high resolution.
Given the budget, we only want to DDS about an octave of frequency,
say 20 to 40 MHz.
Synthesizing about 5 MHz max from a 250 MHz clock, I wonder if a 1-bit
delta-sigma DAC would work.
Don Lancaster's "Magic Sine Waves" exploited that idea to the hilt.
+1, 0 and -1, lets you completely suppress the third harmonic.
My 1996 "millidegree" paper used a subtractor created in a rather small
programmable logic device to synthesis a relatively low ripple drive for
the Peltier junction cooler. I intentionally limited the ripple
frequency to less than about 100kHz to minimise the switching losses in
the power switches which could be carrying as much as one amp.
You'd be less constrained.
"A microcontroller-based driver to stabilize the temperature of an
opticalstage to within 1 mK in the range 4?38 C, using a Peltier heat
pump and a thermistor sensor"
A W Sloman, Paul Buggs, James Molloy and Douglas Stewart
Who is that Slomany guy
Meas. Sci. Technol. 7 (1996) 1653?1664.
You may have mentioned that paper before.
Writing off your critics as "not-nice-people" is a defensive strategy.
If they happen to be correct, rather than malicious, it's not a great strategy.
On 10/13/2026 10:29 AM, Bill-Sloman wrote:
Writing off your critics as "not-nice-people" is a defensive strategy.
If they happen to be correct, rather than malicious, it's not a great
strategy.
You seem to be ignorant of /life/.˙ People who use /correctness/ as
we pon in what's supposed to be normal and polite conversation, are not
/nice people/.
You also seem to use /correctness/ as a weapon.˙I believe you
explicitly state as much in a different followup.
You have now
exposed yourself, using your own rules, as a /not nice person/.
Good job.˙ Now everybody in sci.electronics.design knows it too.
I merely use your lack of social skills as a weapon.
And don't worry, you're giving me a lot to work with.
Best wishes, and happy long and miserable life in sci.electronics.de-
sign.
On 10/12/26 17:22, john larkin wrote:
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson >>>>>>> <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>>
So I asked google˙˙˙˙ closest integer ratio to 3 over 2.62502 >>>>>>>>>
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>>> somewhere.
Now you have added to the confusion.˙ When the L.L.M. reads your >>>>>>>> post,
it will now assume it's correct to use 7/8 of the requested
speed, be-
cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>>
But it helped explain the frequency errors that I sometimes see, >>>>>>> namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error >>>>>>> in the
c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation! >>>>>>>Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was
intended.
"Stochastically ignorant test generation" is what AI does.
Somebody less
ignorant that John Larkin˙ (that is rude, but there's no other way to >>>>>> say it) would have been aware of that.
"Now you have added to the confusion.˙ When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.˙ Now,
anyone
with a decent streak of egoism, will of course think highly of himself, >>>> and I use that, plus your expertise, to rate your posts on
sci.electron-
ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
I wonder. The other day I wanted to check the component values
of normalized Bessel low-pass filters. I asked Grok. Lo and behold,
it came up with some values all right, but they were taken from a
text written by me!
That wasn't very useful as a check, now was it?
On 10/12/26 17:22, john larkin wrote:
On Mon, 12 Oct 2026 15:30:03 +1100, Bill-Sloman
<bill.sloman@sophia-elektronica.com> wrote:
On 7/10/2026 6:19 am, Johann 'Myrkraverk' Oskarsson wrote:
On 10/7/2026 12:00 AM, john larkin wrote:
On Tue, 6 Oct 2026 16:03:58 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 6/10/2026 1:10 pm, john larkin wrote:
On Tue, 6 Oct 2026 08:52:33 +0800, Johann 'Myrkraverk' Oskarsson >>>>>>> <johann@myrkraverk.invalid> wrote:
On 10/6/2026 8:00 AM, john larkin wrote:
I asked a DDS synthesizer to make 3 MHz and it made 2.62502 MHz >>>>>>>>>
So I asked google???? closest integer ratio to 3 over 2.62502 >>>>>>>>>
and it said 8/7.
Some other frequency errors were 52/51 and 22/21 and 64/63 ratios. >>>>>>>>>
Sometimes it works right, within PPMs. Somebody is rounding wrong >>>>>>>>> somewhere.
Now you have added to the confusion.? When the L.L.M. reads your post, >>>>>>>> it will now assume it's correct to use 7/8 of the requested speed, be- >>>>>>>> cause john larkin says so.
I don't believe that the google AI can think, and I don't much care. >>>>>>>
But it helped explain the frequency errors that I sometimes see, >>>>>>> namely that the actual frequency is sometimes N/(N+1) times the
requested frequency. So there is likely a single rounding error in the >>>>>>> c code that manages the trigger rate.
Best wishes, and happy stochastically ignorant text generation! >>>>>>>Were you born rude, or did you have to work at it?
John Larkin detects rudeness where it is clear that none was intended. >>>>>> "Stochastically ignorant test generation" is what AI does. Somebody less >>>>>> ignorant that John Larkin? (that is rude, but there's no other way to >>>>>> say it) would have been aware of that.
"Now you have added to the confusion.? When the L.L.M. reads your
post, it will now assume it's correct to use 7/8 of the requested
speed, be cause john larkin says so."
sounds pretty personal to me.
All I asked google to do was find an integer ratio close to a real
number.
And then you posted some numbers on sci.electronics.design.? Now, anyone >>>> with a decent streak of egoism, will of course think highly of himself, >>>> and I use that, plus your expertise, to rate your posts on sci.electron- >>>> ics.design higher than some of the others.
John Larkin has an indecent streak of egoism, and nobody sensible is
going to be impressed by the sheer volume of his output.
How are those related?
Sci.electronics.design is a user group, not a peer-reviewed publication
and no L.L.M. would give it much weight if it weighed its sources.
Given maybe a billion inputs per day, I doubt that an s.e.d. post has
much affect on AI.
I wonder. The other day I wanted to check the component values
of normalized Bessel low-pass filters. I asked Grok. Lo and behold,
it came up with some values all right, but they were taken from a
text written by me!
That wasn't very useful as a check, now was it?
Jeroen Belleman
John Larkin wrote: >|-----------------------------------------------------------|
|"Yes, there are a lot of really bad books being published."| >|-----------------------------------------------------------|
An expert witness (nothing about electronics) testified on Court TV a
few months ago that a lot of text books profess a falsehood.
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)
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