Forum: Jacob's Hideout BBS

Re: fast flop NB7V52

From Edward Rawde@3:633/10 to All on Thursday, July 16, 2026 14:27:24

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous
logic need not be. Every flip-flop is in fact a little asynchronous
state machine. Every logic designer should try his hand at designing
a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up
next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

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TEXT -728 1680 Left 2 !.tran 0 20m 0 100u startup
TEXT -728 1736 Left 2 !.options plotwinsize=0 numdgt=15
TEXT -1176 528 Left 2 !.MODEL N_1u NMOS LEVEL = 3\n+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 PHI = 0.7 VTO = 0.8 DELTA = 3.0 UO =
650\n+ ETA = 3.0E-6 THETA = 0.1 KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 RSH = 0 NFS = 1E12\n+ TPG = 1 XJ = 500E-9 LD = 100E-9 CGDO =
200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB = 1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5\n*
\n.MODEL P_1u PMOS LEVEL = 3\n+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 PHI = 0.7 VTO = -0.9 DELTA = 0.1 UO = 250\n+ ETA = 0 THETA
= 0.1 KP = 40E-6 VMAX = 5E4 KAPPA = 1 RSH = 0 NFS = 1E12\n+ TPG = -1 XJ = 500E-9 LD = 100E-9 CGDO = 200E-12 CGSO = 200E-12 CGBO =
1E-10\n+ CJ = 400E-6 PB = 1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5
TEXT -1168 456 Left 2 ;Models from cmosedu.com
TEXT -168 3040 Left 2 ;D
TEXT -1168 368 Left 2 ;Edge triggered D type latch in CMOS\nER July 2026

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 12:12:13

"Edward Rawde" <invalid@invalid.invalid> wrote in message news:113b7qe$2vml$1@nnrp.usenet.blueworldhosting.com...

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]

DTL works too, and you can mix it with CMOS.
How many recent EE grads will think two diodes and a resistor if they
need a very slow AND gate?

Version 4.1
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TEXT -728 1680 Left 2 !.tran 0 20m 0 100u startup
TEXT -728 1736 Left 2 !.options plotwinsize=0 numdgt=15
TEXT -1176 528 Left 2 !.MODEL N_1u NMOS LEVEL = 3\n+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 PHI = 0.7 VTO = 0.8 DELTA = 3.0 UO =
650\n+ ETA = 3.0E-6 THETA = 0.1 KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 RSH = 0 NFS = 1E12\n+ TPG = 1 XJ = 500E-9 LD = 100E-9 CGDO =
200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB = 1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5\n* \n.MODEL P_1u PMOS LEVEL = 3\n+
TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 PHI = 0.7 VTO = -0.9 DELTA = 0.1 UO = 250\n+ ETA = 0 THETA = 0.1 KP = 40E-6 VMAX = 5E4
KAPPA = 1 RSH = 0 NFS = 1E12\n+ TPG = -1 XJ = 500E-9 LD = 100E-9 CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB =
1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5
TEXT -1168 456 Left 2 ;Models from cmosedu.com
TEXT -168 3040 Left 2 ;D
TEXT -1168 368 Left 2 ;Edge triggered D type latch in CMOS\nER July 2026

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Saturday, July 18, 2026 02:54:10

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you
proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do >>>> you think that they do it?

They don't.

They use timing information to located positions on the earth surface
with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30
centimeters (12 in), while those for high-end applications such as
engineering and land surveying are accurate to within 2 cm (3?4 in) and
can even provide sub-millimeter accuracy with long-term measurement."

You may not know how they do it, nor be able to do anything that works
quite as well, but while "They don't" may be kind of answer you can
understand it's not one that suggests that you know what you are talking
about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand
what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab
made it perfect clear that the author thought that their gear provided a common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility.

You don't seem to be able to understand what this involved. It certainly
isn't serving up the same clock to any of the D-type bistables involved.

I know people who are committed to single-point grounding too. We
could pick a common point and ground everything to that. I suggest 0/0 latitide and longitude, or maybe a copper rod in the courtyard of the
Royal Observatory in Greenwich.

Again, a lunatic misunderstanding of what is being discussed.

Visit the Royal if you can. It's cool.

I lived in England for 22 years and resisted the temptation. I did visit
the Royal Society once when my wife was being inducted as a fellow - the process spread over three days and was a lot of fun. The fact that my
post-doc supervisor got in in the same batch added a little.

Ray Dyson - the vacuum cleaner man - got an honorary fellowship in that
same batch - but we didn't know at the time that his brother had been a
friend of ours in Cambridge.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Friday, July 17, 2026 19:24:30

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous
logic need not be. Every flip-flop is in fact a little asynchronous
state machine. Every logic designer should try his hand at designing
a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up
next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

That said, I have a 13-gate divide-by-three design which I tried
to simulate in LTspice. Although it *does* divide by three, it also
contains a flaw which I haven't fixed yet. More later.

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Friday, July 17, 2026 10:37:34

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you
proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do >>>>> you think that they do it?

They don't.

They use timing information to located positions on the earth surface
with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30
centimeters (12 in), while those for high-end applications such as
engineering and land surveying are accurate to within 2 cm (3?4 in) and
can even provide sub-millimeter accuracy with long-term measurement."

You may not know how they do it, nor be able to do anything that works
quite as well, but while "They don't" may be kind of answer you can
understand it's not one that suggests that you know what you are talking >>> about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand
what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an
interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab
made it perfect clear that the author thought that their gear provided a >common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing
signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

You don't seem to be able to understand what this involved. It certainly >isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and
designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You have a pathological need to insult, even when it makes no sense.

Curious.

I know people who are committed to single-point grounding too. We
could pick a common point and ground everything to that. I suggest 0/0
latitide and longitude, or maybe a copper rod in the courtyard of the
Royal Observatory in Greenwich.

Again, a lunatic misunderstanding of what is being discussed.

Visit the Royal if you can. It's cool.

I lived in England for 22 years and resisted the temptation. I did visit
the Royal Society once when my wife was being inducted as a fellow - the >process spread over three days and was a lot of fun. The fact that my >post-doc supervisor got in in the same batch added a little.

Brave of you to resist temptation.

There's an RAF museum north of London that you are lucky to have
avoided too.

Ray Dyson - the vacuum cleaner man - got an honorary fellowship in that
same batch - but we didn't know at the time that his brother had been a >friend of ours in Cambridge.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 13:47:29

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous
logic need not be. Every flip-flop is in fact a little asynchronous
state machine. Every logic designer should try his hand at designing >>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up
next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

Divide by 3 in 13 gates sounds like a challenge. I'd set up two
d-types with the relevant feedback and then look for simplifications
such as multi-level combinatorial methods.

That said, I have a 13-gate divide-by-three design which I tried
to simulate in LTspice. Although it *does* divide by three, it also
contains a flaw which I haven't fixed yet. More later.

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From joegwinn@3:633/10 to All on Friday, July 17, 2026 14:39:20

On Fri, 17 Jul 2026 10:37:34 -0700, john larkin <jl@htigct.com> wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you
proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do >>>>>> you think that they do it?

They don't.

They use timing information to located positions on the earth surface
with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30
centimeters (12 in), while those for high-end applications such as
engineering and land surveying are accurate to within 2 cm (3?4 in) and >>>> can even provide sub-millimeter accuracy with long-term measurement."

You may not know how they do it, nor be able to do anything that works >>>> quite as well, but while "They don't" may be kind of answer you can
understand it's not one that suggests that you know what you are talking >>>> about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an
interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab
made it perfect clear that the author thought that their gear provided a >>common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing
signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

You don't seem to be able to understand what this involved. It certainly >>isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and
designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You have a pathological need to insult, even when it makes no sense.

Curious.

Why feed the troll? They live for attention.

Joe

I know people who are committed to single-point grounding too. We
could pick a common point and ground everything to that. I suggest 0/0
latitide and longitude, or maybe a copper rod in the courtyard of the
Royal Observatory in Greenwich.

Again, a lunatic misunderstanding of what is being discussed.

Visit the Royal if you can. It's cool.

I lived in England for 22 years and resisted the temptation. I did visit >>the Royal Society once when my wife was being inducted as a fellow - the >>process spread over three days and was a lot of fun. The fact that my >>post-doc supervisor got in in the same batch added a little.

Brave of you to resist temptation.

There's an RAF museum north of London that you are lucky to have
avoided too.

Ray Dyson - the vacuum cleaner man - got an honorary fellowship in that >>same batch - but we didn't know at the time that his brother had been a >>friend of ours in Cambridge.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 15:13:13

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous
logic need not be. Every flip-flop is in fact a little asynchronous
state machine. Every logic designer should try his hand at designing >>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

[...]

Here's divide by 3 in CMOS in 13 gates.
It does make certain assumptions so please tell me whether those are cheating or not.
There's also a simulation warning but it doesn't stop it simulating.
I'll do it in LTSpice gates when I can get them to work.

Version 4.1
SHEET 1 4068 3392
WIRE 880 -704 880 -768
WIRE 880 -704 848 -704
WIRE 1184 -704 1152 -704
WIRE 1248 -704 1248 -768
WIRE 1248 -704 1184 -704
WIRE 1312 -704 1248 -704
WIRE 1344 -704 1312 -704
WIRE 880 -656 880 -704
WIRE 1152 -656 1152 -704
WIRE 1344 -656 1344 -704
WIRE 976 -640 928 -640
WIRE 1104 -640 1040 -640
WIRE 1440 -640 1392 -640
WIRE 848 -608 848 -704
WIRE 880 -608 848 -608
WIRE 1184 -608 1184 -704
WIRE 1184 -608 1152 -608
WIRE 1312 -608 1312 -704
WIRE 1344 -608 1312 -608
WIRE 880 -528 880 -560
WIRE 880 -528 -96 -528
WIRE 976 -528 976 -640
WIRE 1152 -528 1152 -560
WIRE 1152 -528 976 -528
WIRE 1248 -528 1152 -528
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WIRE 880 -480 880 -528
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WIRE 1248 -432 1200 -432
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WIRE 976 -400 976 -528
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WIRE 1440 -400 1440 -640
WIRE 1440 -400 1296 -400
WIRE 4064 -400 1440 -400
WIRE 880 -352 880 -384
WIRE 1040 -336 1040 -640
WIRE 1440 -336 1040 -336
WIRE 1248 -304 1248 -384
WIRE 1248 -256 1200 -256
WIRE 1200 -240 1200 -256
WIRE 1440 -224 1440 -336
WIRE 1440 -224 1296 -224
WIRE 1648 -224 1440 -224
WIRE 224 -192 192 -192
WIRE 288 -192 288 -256
WIRE 288 -192 224 -192
WIRE 352 -192 288 -192
WIRE 384 -192 352 -192
WIRE 1248 -192 1248 -208
WIRE 2496 -192 2464 -192
WIRE 2560 -192 2560 -256
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WIRE 2656 -192 2624 -192
WIRE 192 -144 192 -192
WIRE 384 -144 384 -192
WIRE 2464 -144 2464 -192
WIRE 2656 -144 2656 -192
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WIRE 496 -128 432 -128
WIRE 2416 -128 2368 -128
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WIRE 224 -96 224 -192
WIRE 224 -96 192 -96
WIRE 352 -96 352 -192
WIRE 384 -96 352 -96
WIRE 2496 -96 2496 -192
WIRE 2496 -96 2464 -96
WIRE 2624 -96 2624 -192
WIRE 2656 -96 2624 -96
WIRE 192 -16 192 -48
WIRE 288 -16 192 -16
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WIRE 384 -16 288 -16
WIRE 560 -16 384 -16
WIRE 2464 -16 2464 -48
WIRE 2560 -16 2464 -16
WIRE 2656 -16 2656 -48
WIRE 2656 -16 2560 -16
WIRE 2832 -16 2656 -16
WIRE 288 32 288 -16
WIRE 2560 32 2560 -16
WIRE 336 80 288 80
WIRE 2608 80 2560 80
WIRE 336 96 336 80
WIRE 2608 96 2608 80
WIRE 96 112 96 -128
WIRE 96 112 32 112
WIRE 240 112 96 112
WIRE 2368 112 2368 -128
WIRE 2368 112 2304 112
WIRE 2512 112 2368 112
WIRE 496 176 496 -128
WIRE 496 176 96 176
WIRE 2768 176 2768 -128
WIRE 2768 176 2368 176
WIRE 288 208 288 128
WIRE 2560 208 2560 128
WIRE 336 256 288 256
WIRE 2608 256 2560 256
WIRE 336 272 336 256
WIRE 2608 272 2608 256
WIRE 96 288 96 176
WIRE 240 288 96 288
WIRE 2368 288 2368 176
WIRE 2512 288 2368 288
WIRE 288 320 288 304
WIRE 2560 320 2560 304
WIRE 96 384 96 288
WIRE 560 384 560 -16
WIRE 2368 384 2368 288
WIRE 2832 384 2832 -16
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WIRE 1120 544 1120 480
WIRE 1120 544 1056 544
WIRE 1184 544 1120 544
WIRE 1216 544 1184 544
WIRE 3328 544 3296 544
WIRE 3392 544 3392 480
WIRE 3392 544 3328 544
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WIRE 3488 544 3456 544
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WIRE 560 560 96 384
WIRE 2368 560 2832 384
WIRE 2832 560 2368 384
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WIRE 1216 592 1216 544
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WIRE 3488 592 3488 544
WIRE 976 608 928 608
WIRE 1328 608 1264 608
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WIRE 1216 640 1184 640
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WIRE 288 672 224 672
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WIRE 1216 720 1216 688
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WIRE 144 736 96 736
WIRE 496 736 432 736
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WIRE 1168 816 1120 816
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WIRE 1168 832 1168 816
WIRE 3440 832 3440 816
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WIRE 288 848 192 848
WIRE 384 848 384 816
WIRE 384 848 288 848
WIRE 560 848 560 560
WIRE 560 848 384 848
WIRE 928 848 928 608
WIRE 928 848 560 848
WIRE 1072 848 928 848
WIRE 2464 848 2464 816
WIRE 2560 848 2464 848
WIRE 2656 848 2656 816
WIRE 2656 848 2560 848
WIRE 2832 848 2832 560
WIRE 2832 848 2656 848
WIRE 3200 848 3200 608
WIRE 3200 848 2832 848
WIRE 3344 848 3200 848
WIRE 288 896 288 848
WIRE 2560 896 2560 848
WIRE 1328 912 1328 608
WIRE 1328 912 928 912
WIRE 3600 912 3600 608
WIRE 3600 912 3200 912
WIRE 336 944 288 944
WIRE 1120 944 1120 864
WIRE 2608 944 2560 944
WIRE 3392 944 3392 864
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WIRE 2608 960 2608 944
WIRE 96 976 96 736
WIRE 240 976 96 976
WIRE 2368 976 2368 736
WIRE 2512 976 2368 976
WIRE 1168 992 1120 992
WIRE 3440 992 3392 992
WIRE 1168 1008 1168 992
WIRE 3440 1008 3440 992
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WIRE 1072 1024 928 1024
WIRE 3200 1024 3200 912
WIRE 3344 1024 3200 1024
WIRE 496 1040 496 736
WIRE 496 1040 96 1040
WIRE 2768 1040 2768 736
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WIRE 2560 1072 2560 992
WIRE 336 1120 288 1120
WIRE 928 1120 928 1024
WIRE 1392 1120 1392 720
WIRE 2608 1120 2560 1120
WIRE 3200 1120 3200 1024
WIRE 3664 1120 3664 720
WIRE 336 1136 336 1120
WIRE 2608 1136 2608 1120
WIRE 96 1152 96 1040
WIRE 96 1152 -640 1152
WIRE 240 1152 96 1152
WIRE 2368 1152 2368 1040
WIRE 2368 1152 2000 1152
WIRE 2512 1152 2368 1152
WIRE 288 1184 288 1168
WIRE 2560 1184 2560 1168
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WIRE -880 1264 -912 1264
WIRE -832 1264 -880 1264
WIRE 928 1296 1392 1120
WIRE 1392 1296 928 1120
WIRE 3200 1296 3664 1120
WIRE 3664 1296 3200 1120
WIRE -912 1312 -912 1264
WIRE 96 1392 560 1216
WIRE 2368 1392 2832 1216
WIRE 1056 1408 1024 1408
WIRE 1120 1408 1120 1344
WIRE 1120 1408 1056 1408
WIRE 1184 1408 1120 1408
WIRE 1216 1408 1184 1408
WIRE 3328 1408 3296 1408
WIRE 3392 1408 3392 1344
WIRE 3392 1408 3328 1408
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WIRE 3488 1408 3456 1408
WIRE -912 1440 -912 1392
WIRE 1024 1456 1024 1408
WIRE 1216 1456 1216 1408
WIRE 3296 1456 3296 1408
WIRE 3488 1456 3488 1408
WIRE 928 1472 928 1296
WIRE 976 1472 928 1472
WIRE 1328 1472 1264 1472
WIRE 3200 1472 3200 1296
WIRE 3248 1472 3200 1472
WIRE 3600 1472 3536 1472
WIRE 1056 1504 1056 1408
WIRE 1056 1504 1024 1504
WIRE 1184 1504 1184 1408
WIRE 1216 1504 1184 1504
WIRE 3328 1504 3328 1408
WIRE 3328 1504 3296 1504
WIRE 3456 1504 3456 1408
WIRE 3488 1504 3456 1504
WIRE 224 1520 192 1520
WIRE 288 1520 288 1456
WIRE 288 1520 224 1520
WIRE 352 1520 288 1520
WIRE 384 1520 352 1520
WIRE 544 1520 384 1520
WIRE 576 1520 544 1520
WIRE 2496 1520 2464 1520
WIRE 2560 1520 2560 1456
WIRE 2560 1520 2496 1520
WIRE 2624 1520 2560 1520
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WIRE 2816 1520 2656 1520
WIRE 2848 1520 2816 1520
WIRE 192 1568 192 1520
WIRE 384 1568 384 1520
WIRE 576 1568 576 1520
WIRE 2464 1568 2464 1520
WIRE 2656 1568 2656 1520
WIRE 2848 1568 2848 1520
WIRE 96 1584 96 1392
WIRE 144 1584 96 1584
WIRE 496 1584 432 1584
WIRE 688 1584 624 1584
WIRE 1024 1584 1024 1552
WIRE 1120 1584 1024 1584
WIRE 1216 1584 1216 1552
WIRE 1216 1584 1120 1584
WIRE 1392 1584 1392 1296
WIRE 1392 1584 1216 1584
WIRE 1488 1584 1392 1584
WIRE 1648 1584 1648 -224
WIRE 1648 1584 1488 1584
WIRE 2368 1584 2368 1392
WIRE 2416 1584 2368 1584
WIRE 2768 1584 2704 1584
WIRE 2960 1584 2896 1584
WIRE 3296 1584 3296 1552
WIRE 3392 1584 3296 1584
WIRE 3488 1584 3488 1552
WIRE 3488 1584 3392 1584
WIRE 3664 1584 3664 1296
WIRE 3664 1584 3488 1584
WIRE 3760 1584 3664 1584
WIRE 4064 1584 4064 -400
WIRE 4064 1584 3760 1584
WIRE 224 1616 224 1520
WIRE 224 1616 192 1616
WIRE 352 1616 352 1520
WIRE 384 1616 352 1616
WIRE 544 1616 544 1520
WIRE 576 1616 544 1616
WIRE 2496 1616 2496 1520
WIRE 2496 1616 2464 1616
WIRE 2624 1616 2624 1520
WIRE 2656 1616 2624 1616
WIRE 2816 1616 2816 1520
WIRE 2848 1616 2816 1616
WIRE 1120 1632 1120 1584
WIRE 3392 1632 3392 1584
WIRE 1168 1680 1120 1680
WIRE 3440 1680 3392 1680
WIRE 192 1696 192 1664
WIRE 288 1696 192 1696
WIRE 384 1696 384 1664
WIRE 384 1696 288 1696
WIRE 576 1696 576 1664
WIRE 576 1696 384 1696
WIRE 768 1696 576 1696
WIRE 1168 1696 1168 1680
WIRE 2464 1696 2464 1664
WIRE 2560 1696 2464 1696
WIRE 2656 1696 2656 1664
WIRE 2656 1696 2560 1696
WIRE 2848 1696 2848 1664
WIRE 2848 1696 2656 1696
WIRE 3040 1696 2848 1696
WIRE 3440 1696 3440 1680
WIRE 928 1712 928 1472
WIRE 1072 1712 928 1712
WIRE 3200 1712 3200 1472
WIRE 3344 1712 3200 1712
WIRE 288 1744 288 1696
WIRE 2560 1744 2560 1696
WIRE 1328 1776 1328 1472
WIRE 1328 1776 928 1776
WIRE 3600 1776 3600 1472
WIRE 3600 1776 3200 1776
WIRE 336 1792 288 1792
WIRE 2608 1792 2560 1792
WIRE 336 1808 336 1792
WIRE 1120 1808 1120 1728
WIRE 2608 1808 2608 1792
WIRE 3392 1808 3392 1728
WIRE 96 1824 96 1584
WIRE 240 1824 96 1824
WIRE 2368 1824 2368 1584
WIRE 2512 1824 2368 1824
WIRE 1168 1856 1120 1856
WIRE 3440 1856 3392 1856
WIRE 1168 1872 1168 1856
WIRE 3440 1872 3440 1856
WIRE 496 1888 496 1584
WIRE 496 1888 96 1888
WIRE 768 1888 768 1696
WIRE 928 1888 928 1776
WIRE 928 1888 768 1888
WIRE 1072 1888 928 1888
WIRE 2768 1888 2768 1584
WIRE 2768 1888 2368 1888
WIRE 3040 1888 3040 1696
WIRE 3200 1888 3200 1776
WIRE 3200 1888 3040 1888
WIRE 3344 1888 3200 1888
WIRE 288 1920 288 1840
WIRE 1120 1920 1120 1904
WIRE 2560 1920 2560 1840
WIRE 3392 1920 3392 1904
WIRE 336 1968 288 1968
WIRE 2608 1968 2560 1968
WIRE 336 1984 336 1968
WIRE 2608 1984 2608 1968
WIRE -640 2000 -640 1152
WIRE 96 2000 96 1888
WIRE 96 2000 -640 2000
WIRE 240 2000 96 2000
WIRE 2000 2000 2000 1152
WIRE 2368 2000 2368 1888
WIRE 2368 2000 2000 2000
WIRE 2512 2000 2368 2000
WIRE 688 2064 688 1584
WIRE 688 2064 96 2064
WIRE 2960 2064 2960 1584
WIRE 2960 2064 2368 2064
WIRE 288 2096 288 2016
WIRE 2560 2096 2560 2016
WIRE 336 2144 288 2144
WIRE 2608 2144 2560 2144
WIRE 336 2160 336 2144
WIRE 2608 2160 2608 2144
WIRE -976 2176 -1040 2176
WIRE -640 2176 -640 2000
WIRE -640 2176 -976 2176
WIRE 96 2176 96 2064
WIRE 240 2176 96 2176
WIRE 2368 2176 2368 2064
WIRE 2512 2176 2368 2176
WIRE 288 2208 288 2192
WIRE 2560 2208 2560 2192
WIRE -1040 2272 -1040 2176
WIRE 96 2272 96 2176
WIRE 768 2272 768 1888
WIRE 768 2272 560 2272
WIRE 2368 2272 2368 2176
WIRE 3040 2272 3040 1888
WIRE 3040 2272 2832 2272
WIRE -1040 2416 -1040 2352
WIRE 96 2448 560 2272
WIRE 560 2448 96 2272
WIRE 2368 2448 2832 2272
WIRE 2832 2448 2368 2272
WIRE 224 2576 192 2576
WIRE 288 2576 288 2512
WIRE 288 2576 224 2576
WIRE 352 2576 288 2576
WIRE 384 2576 352 2576
WIRE 2496 2576 2464 2576
WIRE 2560 2576 2560 2512
WIRE 2560 2576 2496 2576
WIRE 2624 2576 2560 2576
WIRE 2656 2576 2624 2576
WIRE 192 2624 192 2576
WIRE 384 2624 384 2576
WIRE 2464 2624 2464 2576
WIRE 2656 2624 2656 2576
WIRE 96 2640 96 2448
WIRE 144 2640 96 2640
WIRE 496 2640 432 2640
WIRE 2368 2640 2368 2448
WIRE 2416 2640 2368 2640
WIRE 2768 2640 2704 2640
WIRE 224 2672 224 2576
WIRE 224 2672 192 2672
WIRE 352 2672 352 2576
WIRE 384 2672 352 2672
WIRE 2496 2672 2496 2576
WIRE 2496 2672 2464 2672
WIRE 2624 2672 2624 2576
WIRE 2656 2672 2624 2672
WIRE 192 2752 192 2720
WIRE 288 2752 192 2752
WIRE 384 2752 384 2720
WIRE 384 2752 288 2752
WIRE 560 2752 560 2448
WIRE 560 2752 384 2752
WIRE 2464 2752 2464 2720
WIRE 2560 2752 2464 2752
WIRE 2656 2752 2656 2720
WIRE 2656 2752 2560 2752
WIRE 2832 2752 2832 2448
WIRE 2832 2752 2656 2752
WIRE 288 2800 288 2752
WIRE 2560 2800 2560 2752
WIRE 336 2848 288 2848
WIRE 2608 2848 2560 2848
WIRE 336 2864 336 2848
WIRE 2608 2864 2608 2848
WIRE 96 2880 96 2640
WIRE 240 2880 96 2880
WIRE 2368 2880 2368 2640
WIRE 2512 2880 2368 2880
WIRE 496 2944 496 2640
WIRE 496 2944 96 2944
WIRE 2768 2944 2768 2640
WIRE 2768 2944 2368 2944
WIRE 288 2976 288 2896
WIRE 2560 2976 2560 2896
WIRE 336 3024 288 3024
WIRE 2608 3024 2560 3024
WIRE 336 3040 336 3024
WIRE 2608 3040 2608 3024
WIRE -96 3056 -96 -528
WIRE 96 3056 96 2944
WIRE 96 3056 -96 3056
WIRE 240 3056 96 3056
WIRE 1872 3056 1872 720
WIRE 2368 3056 2368 2944
WIRE 2368 3056 1872 3056
WIRE 2512 3056 2368 3056
WIRE 288 3088 288 3072
WIRE 2560 3088 2560 3072
WIRE 32 3152 32 112
WIRE 560 3152 560 2752
WIRE 560 3152 32 3152
WIRE 2304 3152 2304 112
WIRE 2832 3152 2832 2752
WIRE 2832 3152 2304 3152
WIRE -640 3248 -640 2176
WIRE 2000 3248 2000 2000
WIRE 2000 3248 -640 3248
FLAG -912 1440 0
FLAG -880 1264 Vdd
FLAG 288 -256 Vdd
FLAG 288 320 0
FLAG 336 96 0
FLAG 336 272 0
FLAG 288 1184 0
FLAG 336 960 0
FLAG 336 1136 0
FLAG 336 1808 0
FLAG 336 1984 0
FLAG 288 2208 0
FLAG 336 2160 0
FLAG 288 3088 0
FLAG 336 2864 0
FLAG 336 3040 0
FLAG 1120 1056 0
FLAG 1168 832 0
FLAG 1168 1008 0
FLAG 1120 1920 0
FLAG 1168 1696 0
FLAG 1168 1872 0
FLAG -1040 2416 0
FLAG 288 608 Vdd
FLAG 1120 480 Vdd
FLAG 288 1456 Vdd
FLAG 1120 1344 Vdd
FLAG 288 2512 Vdd
FLAG -976 2176 Ck
FLAG 1456 720 Q0
FLAG 1488 1584 Qbar0
FLAG 2560 -256 Vdd
FLAG 2560 320 0
FLAG 2608 96 0
FLAG 2608 272 0
FLAG 2560 1184 0
FLAG 2608 960 0
FLAG 2608 1136 0
FLAG 2608 1808 0
FLAG 2608 1984 0
FLAG 2560 2208 0
FLAG 2608 2160 0
FLAG 2560 3088 0
FLAG 2608 2864 0
FLAG 2608 3040 0
FLAG 3392 1056 0
FLAG 3440 832 0
FLAG 3440 1008 0
FLAG 3392 1920 0
FLAG 3440 1696 0
FLAG 3440 1872 0
FLAG 2560 608 Vdd
FLAG 3392 480 Vdd
FLAG 2560 1456 Vdd
FLAG 3392 1344 Vdd
FLAG 2560 2512 Vdd
FLAG 3728 720 Q1
FLAG 3760 1584 Qbar1
FLAG 1248 -768 Vdd
FLAG 1248 -192 0
FLAG 1200 -416 0
FLAG 1200 -240 0
FLAG 832 -416 0
FLAG 880 -352 0
FLAG 880 -768 Vdd
SYMBOL voltage -912 1296 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -1040 2256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10n 10n 1m 2m 10)
SYMBOL pmos4 144 -48 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M1
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 432 -48 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M2
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 32 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M3
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 208 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M4
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 144 816 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M5
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 432 816 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M6
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 896 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M7
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 1072 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M8
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 976 688 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M19
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 1264 688 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M20
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1072 768 R0
WINDOW 0 -47 25 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M21
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1072 944 R0
WINDOW 0 -50 21 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M22
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 144 1664 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M9
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 432 1664 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M10
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 624 1664 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M11
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 1744 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M12
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 1920 R0
WINDOW 0 -46 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M13
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 2096 R0
WINDOW 0 -49 25 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M14
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 976 1552 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M23
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 1264 1552 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M24
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1072 1632 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M25
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1072 1808 R0
WINDOW 0 -46 21 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M26
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 144 2720 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M15
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 432 2720 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M16
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 2800 R0
WINDOW 0 -52 28 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M17
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 240 2976 R0
WINDOW 0 -49 28 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M18
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2416 -48 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M27
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2704 -48 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M28
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2512 32 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M29
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2512 208 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M30
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TEXT -1064 1664 Left 2 !.tran 0 20m 0 100u startup
TEXT -1064 1720 Left 2 !.options plotwinsize=0 numdgt=15
TEXT -1264 448 Left 2 !.MODEL N_1u NMOS LEVEL = 3\n+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 PHI = 0.7 VTO = 0.8 DELTA = 3.0 UO =
650\n+ ETA = 3.0E-6 THETA = 0.1 KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 RSH = 0 NFS = 1E12\n+ TPG = 1 XJ = 500E-9 LD = 100E-9 CGDO =
200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB = 1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5\n* \n.MODEL P_1u PMOS LEVEL = 3\n+
TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 PHI = 0.7 VTO = -0.9 DELTA = 0.1 UO = 250\n+ ETA = 0 THETA = 0.1 KP = 40E-6 VMAX = 5E4
KAPPA = 1 RSH = 0 NFS = 1E12\n+ TPG = -1 XJ = 500E-9 LD = 100E-9 CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB =
1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5
TEXT -1256 376 Left 2 ;Models from cmosedu.com
TEXT -1256 288 Left 2 ;Divide by 3\nER July 2026
TEXT 936 -264 Left 2 ;AND gate

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Friday, July 17, 2026 12:59:24

On Fri, 17 Jul 2026 14:39:20 -0400, joegwinn@comcast.net wrote:

On Fri, 17 Jul 2026 10:37:34 -0700, john larkin <jl@htigct.com> wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org> >>wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you
proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface >>>>> with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30
centimeters (12 in), while those for high-end applications such as
engineering and land surveying are accurate to within 2 cm (3?4 in) and >>>>> can even provide sub-millimeter accuracy with long-term measurement." >>>>>
You may not know how they do it, nor be able to do anything that works >>>>> quite as well, but while "They don't" may be kind of answer you can
understand it's not one that suggests that you know what you are talking >>>>> about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>>what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an
interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab >>>made it perfect clear that the author thought that their gear provided a >>>common clock for the entire foot-ball stadium sized lab, with tight >>>jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing >>signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

You don't seem to be able to understand what this involved. It certainly >>>isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and >>designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You have a pathological need to insult, even when it makes no sense.

Curious.

Why feed the troll? They live for attention.

Joe

Oh, he is a lost cause, but it's a way to have discussions, sometimes
on topic.

SED and usenet in general are almost dead.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Friday, July 17, 2026 13:03:41

On Fri, 17 Jul 2026 13:47:29 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>> state machine. Every logic designer should try his hand at designing >>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up
next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

Divide by 3 in 13 gates sounds like a challenge. I'd set up two
d-types with the relevant feedback and then look for simplifications
such as multi-level combinatorial methods.

That said, I have a 13-gate divide-by-three design which I tried
to simulate in LTspice. Although it *does* divide by three, it also
contains a flaw which I haven't fixed yet. More later.

Jeroen Belleman

ltspice digital parts are kinda terrible. If you don't add a prop
delay parameter, they can act non-causal.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 16:27:20

"john larkin" <jl@htigct.com> wrote in message news:0h2l5l9msifvpcijusdva41r08t4evr31i@4ax.com...

On Fri, 17 Jul 2026 13:47:29 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

Divide by 3 in 13 gates sounds like a challenge. I'd set up two
d-types with the relevant feedback and then look for simplifications
such as multi-level combinatorial methods.

That said, I have a 13-gate divide-by-three design which I tried
to simulate in LTspice. Although it *does* divide by three, it also
contains a flaw which I haven't fixed yet. More later.

Jeroen Belleman

ltspice digital parts are kinda terrible. If you don't add a prop
delay parameter, they can act non-causal.

Thanks. Now the simulation runs but this wasn't intended to be a 50MHz oscillator.
What is going on?

Version 4.1
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TEXT -1264 72 Left 2 !.tran 0 100 0 1n startup

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Friday, July 17, 2026 22:40:32

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>> state machine. Every logic designer should try his hand at designing >>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up
next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Jeroen Belleman
=================================
Version 4
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SYMATTR Value PULSE(0 1 10n 1n 1n 10n 22n)
SYMATTR InstName V1
TEXT -488 104 Left 2 !.tran 200n
TEXT -256 -144 Left 2 ;D-FF divide by two. Jeroen Belleman - 20260717

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 17:35:24

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e400$32u9l$1@dont-email.me...

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Thanks for that.

It appears that the only difference between the circuit I posted and your circuit
is that adding the 1m ohm resistor to my circuit makes it work.

I wouldn't normally leave inputs open circuit but it doesn't seem to be essential
to connect them or the ground symbols. (Who makes a five-input gate anyway?)

Why is that resistor needed and how would I know where to add a resistor
in other simulations?

Version 4.1
SHEET 1 880 680
WIRE 0 -96 -96 -96
WIRE 112 -48 64 -48
WIRE 0 -32 -32 -32
WIRE -32 0 -32 -32
WIRE 112 0 112 -48
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SYMBOL Digital\\and 272 64 R0
SYMATTR InstName A1
SYMBOL Digital\\and 272 208 R0
SYMATTR InstName A2
SYMBOL Digital\\and 32 -128 R0
SYMATTR InstName A3
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WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
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SYMATTR Value 1m
SYMBOL voltage -384 192 R0
WINDOW 3 -97 171 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 1 10n 1n 1n 10n 22n)
SYMATTR InstName V1
TEXT -488 104 Left 2 !.tran 200n
TEXT -256 -168 Left 2 ;D-FF divide by two. Jeroen Belleman - 20260717
TEXT -32 -144 Left 2 ;Modified by ER

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Saturday, July 18, 2026 00:00:45

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>> state machine. Every logic designer should try his hand at designing >>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Here's my divide-by-three. There is something fishy though. Note that
I'm not actually using the delay line T1, yet, without it, simulation
fails. Oh well.

Jeroen Belleman

============================
Version 4
SHEET 1 880 980
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SYMATTR InstName A4
SYMBOL Digital\\and -416 16 R0
SYMATTR InstName A5
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SYMATTR InstName A7
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SYMBOL voltage -1168 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
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SYMATTR Value PULSE(0 1 10n 1n 1n 10n 22n 10)
SYMBOL Digital\\and -416 112 R0
SYMATTR InstName A6
SYMBOL Digital\\and -416 752 R0
SYMATTR InstName A12
SYMBOL res -16 544 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL tline -64 704 R0
SYMATTR InstName T1
TEXT -1040 32 Left 2 !.tran 200n
TEXT 24 112 Left 2 ;Output A is the 1/3 clock output.
TEXT -960 -112 Left 2 ;Asynchronous divide-by-three.
TEXT -424 904 Left 2 ;No idea why simulation fails if T1 is removed.
TEXT -960 -80 Left 2 ;Jeroen Belleman - 20260717
TEXT -424 936 Left 2 ;I'm not actually using it!

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Saturday, July 18, 2026 00:07:16

On 7/17/26 23:35, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e400$32u9l$1@dont-email.me...

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Thanks for that.

It appears that the only difference between the circuit I posted and your circuit
is that adding the 1m ohm resistor to my circuit makes it work.

I wouldn't normally leave inputs open circuit but it doesn't seem to be essential
to connect them or the ground symbols. (Who makes a five-input gate anyway?)

Why is that resistor needed and how would I know where to add a resistor
in other simulations?

Oh, I added that resistor only because you can't give two different
names to the same node. D is effectively connected to nQ.

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Saturday, July 18, 2026 00:16:41

On 7/17/26 22:03, john larkin wrote:

On Fri, 17 Jul 2026 13:47:29 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

Divide by 3 in 13 gates sounds like a challenge. I'd set up two
d-types with the relevant feedback and then look for simplifications
such as multi-level combinatorial methods.

That said, I have a 13-gate divide-by-three design which I tried
to simulate in LTspice. Although it *does* divide by three, it also
contains a flaw which I haven't fixed yet. More later.

Jeroen Belleman

ltspice digital parts are kinda terrible. If you don't add a prop
delay parameter, they can act non-causal.

Ah, I wasn't aware of that. I never simulated logic in LTspice before.
Just adding a spiceline 'Trise=1n Tfall=1n' to elements A1, A2 and A3
fixes my divide-by-three. Delay line T1 can be removed and it still
simulates correctly.

Thanks for the hint!

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From JM@3:633/10 to All on Friday, July 17, 2026 23:16:48

On Sat, 18 Jul 2026 00:00:45 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

Here's my divide-by-three. There is something fishy though. Note that
I'm not actually using the delay line T1, yet, without it, simulation
fails. Oh well.

Jeroen Belleman

You should really tie unused inputs (and outputs) to gate node 8, that
removes them from the simulation.

Version 4.1
SHEET 1 880 1412
WIRE -528 -112 -544 -112
WIRE -448 -112 -528 -112
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TEXT -960 -112 Left 2 ;Asynchronous divide-by-three.
TEXT 360 904 Left 2 ;No idea why simulation fails if T1 is removed.
TEXT -960 -80 Left 2 ;Jeroen Belleman - 20260717
TEXT 360 944 Left 2 ;I'm not actually using it!

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Saturday, July 18, 2026 00:20:57

On 7/17/26 23:35, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e400$32u9l$1@dont-email.me...

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Thanks for that.

It appears that the only difference between the circuit I posted and your circuit
is that adding the 1m ohm resistor to my circuit makes it work.

I wouldn't normally leave inputs open circuit but it doesn't seem to be essential
to connect them or the ground symbols. (Who makes a five-input gate anyway?)

Ah, I see. That cleans it up quite a bit. Thanks!

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Saturday, July 18, 2026 00:30:43

On 7/18/26 00:16, JM wrote:

On Sat, 18 Jul 2026 00:00:45 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

Here's my divide-by-three. There is something fishy though. Note that
I'm not actually using the delay line T1, yet, without it, simulation
fails. Oh well.

Jeroen Belleman

You should really tie unused inputs (and outputs) to gate node 8, that removes them from the simulation.

Version 4.1

[Deleted...]
I see. It's kind of counter-intuitive though, isn't it?

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From JM@3:633/10 to All on Saturday, July 18, 2026 00:04:40

On Sat, 18 Jul 2026 00:30:43 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

You should really tie unused inputs (and outputs) to gate node 8, that
removes them from the simulation.

Version 4.1

[Deleted...]
I see. It's kind of counter-intuitive though, isn't it?

Yes.

Every time I run LTspice it calls to mind the Amy Winehouse line (may
she rest in peace) - "What kind of fuckery is this?"

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 20:18:37

"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:11377b4$u16k$6@dont-email.me...

On 15/07/2026 3:27 am, john larkin wrote:

On Tue, 14 Jul 2026 17:48:26 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:

On 7/14/26 02:47, Bill Sloman wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

..

Sometimes you do need to process externally generated triggers, but in >>>> lots of cases you can avoid it if you try hard enough. Marketing hates >>>> asking customers to even try.

you are joking right??

Why have oscilloscopes that use external triggers? That's some idiotic
marketing thing again.

And that is an idiotic observation.

My first oscilloscope didn't have trig it had sync and I had to wait for the valves to warm up.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Friday, July 17, 2026 21:06:45

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e92k$34idt$2@dont-email.me...

On 7/17/26 23:35, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e400$32u9l$1@dont-email.me...

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race >>>>>>> condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Thanks for that.

It appears that the only difference between the circuit I posted and your circuit
is that adding the 1m ohm resistor to my circuit makes it work.

I wouldn't normally leave inputs open circuit but it doesn't seem to be essential
to connect them or the ground symbols. (Who makes a five-input gate anyway?) >>
Why is that resistor needed and how would I know where to add a resistor
in other simulations?

Oh, I added that resistor only because you can't give two different
names to the same node. D is effectively connected to nQ.

With the alternate solver the resistor has to be at least 1e-19 ohms.
Any lower than that and you get a 50MHz oscillator instead.

If anyone can explain that to me I'm all ears.

Version 4.1
SHEET 1 880 680
WIRE -656 -608 -736 -608
WIRE -656 -576 -704 -576
WIRE -480 -576 -592 -576
WIRE -704 -528 -704 -576
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FLAG -160 -160 Qbar
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WINDOW 3 -37 117 Left 2
SYMATTR Value Td=10n
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TEXT -1264 72 Left 2 !.tran 0 200m 0 100n startup
TEXT -1256 136 Left 2 !.options solver alt

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Friday, July 17, 2026 18:12:57

On Sat, 18 Jul 2026 00:16:41 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 7/17/26 22:03, john larkin wrote:

On Fri, 17 Jul 2026 13:47:29 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid >>>>>>>>> (Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race
condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

Divide by 3 in 13 gates sounds like a challenge. I'd set up two
d-types with the relevant feedback and then look for simplifications
such as multi-level combinatorial methods.

That said, I have a 13-gate divide-by-three design which I tried
to simulate in LTspice. Although it *does* divide by three, it also
contains a flaw which I haven't fixed yet. More later.

Jeroen Belleman

ltspice digital parts are kinda terrible. If you don't add a prop
delay parameter, they can act non-causal.

Ah, I wasn't aware of that. I never simulated logic in LTspice before.
Just adding a spiceline 'Trise=1n Tfall=1n' to elements A1, A2 and A3
fixes my divide-by-three. Delay line T1 can be removed and it still
simulates correctly.

Thanks for the hint!

Jeroen Belleman

Yeah, the obvious shift register won't work without adding prop
delays.

Sounds like adding some rise and fall works too.

Doing any serious logic in LT is still horrible. I tried a DDS phase accumulator and gave up. I wrote a PowerBasic problem to generate a
PWL file and sent that to LT Spice for filtering and such.

Apparently Qspice is much better.

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Saturday, July 18, 2026 15:26:17

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you
proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do >>>>>> you think that they do it?

They don't.

They use timing information to located positions on the earth surface
with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30
centimeters (12 in), while those for high-end applications such as
engineering and land surveying are accurate to within 2 cm (3?4 in) and >>>> can even provide sub-millimeter accuracy with long-term measurement."

You may not know how they do it, nor be able to do anything that works >>>> quite as well, but while "They don't" may be kind of answer you can
understand it's not one that suggests that you know what you are talking >>>> about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand
what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an
interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab
made it perfect clear that the author thought that their gear provided a
common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing
signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic
clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get
there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable.

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly
isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and
designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have
posted above makes clear. Your VME modules hang off it, rather than
contribute to it.

You have a pathological need to insult, even when it makes no sense.

Pointing out that somebody is posting ignorant nonsense is a necessary
part of robust technological debate. Somebody too ignorant to realise
that they are posting ignorant nonsense is going to feel hurt by the observation, but it is necessary to call out ignorance.

Curious.

Not half as curious as a pig-ignorant purveyor of high-tech equipment.

I know people who are committed to single-point grounding too. We
could pick a common point and ground everything to that. I suggest 0/0
latitide and longitude, or maybe a copper rod in the courtyard of the
Royal Observatory in Greenwich.

Again, a lunatic misunderstanding of what is being discussed.

Visit the Royal if you can. It's cool.

I lived in England for 22 years and resisted the temptation. I did visit
the Royal Society once when my wife was being inducted as a fellow - the
process spread over three days and was a lot of fun. The fact that my
post-doc supervisor got in in the same batch added a little.

Brave of you to resist temptation.

The place is full of tourist traps. I wasn't a tourist. Some of my
visiting friends were, but I rarely joined them.

There's an RAF museum north of London that you are lucky to have
avoided too.

Duxford? Drove past it regularly going from London to Cambridge - may
have dropped in once to accommodate a visiting friend, but it didn't
make much of an impression. Nothing I saw was unfamiliar.

https://www.iwm.org.uk/visits/iwm-duxford

<snip>

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Saturday, July 18, 2026 17:31:24

On 18/07/2026 5:59 am, john larkin wrote:

On Fri, 17 Jul 2026 14:39:20 -0400, joegwinn@comcast.net wrote:

On Fri, 17 Jul 2026 10:37:34 -0700, john larkin <jl@htigct.com> wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

You have a pathological need to insult, even when it makes no sense.

Curious.

Why feed the troll? They live for attention.

John Larkin trolls for flattery, but doesn't really know how to bait the
hook.

Oh, he is a lost cause, but it's a way to have discussions, sometimes
on topic.

I'm certainly not going to flatter John Larkin, but he has been known to
hunt for flattery in serious discussions, and sometimes manages to earn
some. He's not a complete idiot.

SED and usenet in general are almost dead.

There are people who can manage serious discussion around the attention seekers. Not all that many, but s.e.d. has a hard core. John Larkin was
our most prolific poster for a long time - and may still be, the
statistics aren't easily available any more - but he didn't get in the
way too much.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Saturday, July 18, 2026 11:44:31

On 7/18/26 03:06, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e92k$34idt$2@dont-email.me...

On 7/17/26 23:35, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e400$32u9l$1@dont-email.me...

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>>>>> state machine. Every logic designer should try his hand at designing >>>>>>>>>> a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race >>>>>>>> condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>>>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask
for a transistor level implementation! The point of the challenge
was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Thanks for that.

It appears that the only difference between the circuit I posted and your circuit
is that adding the 1m ohm resistor to my circuit makes it work.

I wouldn't normally leave inputs open circuit but it doesn't seem to be essential
to connect them or the ground symbols. (Who makes a five-input gate anyway?)

Why is that resistor needed and how would I know where to add a resistor >>> in other simulations?

Oh, I added that resistor only because you can't give two different
names to the same node. D is effectively connected to nQ.

With the alternate solver the resistor has to be at least 1e-19 ohms.
Any lower than that and you get a 50MHz oscillator instead.

If anyone can explain that to me I'm all ears.

I'd think that for any circuit with sufficient gain and delayed
feedback, there will be some frequency at which it can oscillate.

Rather than specifying Td, try specifying Trise and Tfall, or Tau.
That will reduce the bandwidth and should quench it.

In your schematic, I got it to work with Tau=1n for A1 and A2,
Tau=2n for A4, A5 and A8, and Tau=3n for A3. Curiously, with
Tau=2n for all gates, it still misbehaves. I suppose this is
a good demo of why Spice is a poor logic simulator.

Then again, I wouldn't make a D-flop like that.

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Saturday, July 18, 2026 03:21:09

On Sat, 18 Jul 2026 15:26:17 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you
proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface >>>>> with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30
centimeters (12 in), while those for high-end applications such as
engineering and land surveying are accurate to within 2 cm (3?4 in) and >>>>> can even provide sub-millimeter accuracy with long-term measurement." >>>>>
You may not know how they do it, nor be able to do anything that works >>>>> quite as well, but while "They don't" may be kind of answer you can
understand it's not one that suggests that you know what you are talking >>>>> about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand
what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an
interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab
made it perfect clear that the author thought that their gear provided a >>> common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing
signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic
clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get >there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable.

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly >>> isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and
designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have
posted above makes clear. Your VME modules hang off it, rather than >contribute to it.

Well, I helped design the system. It's more interesting than a stirred
water bath.

The VME timing modules use an ECL flop as the clock recovery detector.
It's a bang-bang phase-locked loop with a roughly 1e12 volt/second
slope.

The incoming data stream is the clock of the phase detector flop and
the local XO is D. Sorta backwards. Metastability is the prize for
being right.

Bang-bang PDs are unpopular for some reason.

I confess that I don't understand the loop. I don't need to understand
things, I just need to make them work.

I could post the circuit if there were popular demand.

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Sunday, July 19, 2026 01:16:10

On 18/07/2026 8:21 pm, john larkin wrote:

On Sat, 18 Jul 2026 15:26:17 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you >>>>>>>>> proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface >>>>>> with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30 >>>>>> centimeters (12 in), while those for high-end applications such as >>>>>> engineering and land surveying are accurate to within 2 cm (3?4 in) and >>>>>> can even provide sub-millimeter accuracy with long-term measurement." >>>>>>
You may not know how they do it, nor be able to do anything that works >>>>>> quite as well, but while "They don't" may be kind of answer you can >>>>>> understand it's not one that suggests that you know what you are talking >>>>>> about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>>> what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an >>>>> interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab
made it perfect clear that the author thought that their gear provided a >>>> common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility. >>>

The hundreds of VME modules are frequency-locked to the master timing
signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic
clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get
there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable.

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly >>>> isn't serving up the same clock to any of the D-type bistables involved. >>>

Of course I understand the NIF timing system. I helped design it and
designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have
posted above makes clear. Your VME modules hang off it, rather than
contribute to it.

Well, I helped design the system. It's more interesting than a stirred
water bath.

I've never designed a thermostatted stirred water bath. My 1996 paper
was about Peltier-junction based thermostat. The first version did use circulating water to take away the waste heat from the Peltier
junctions, but one of colleagues replaced that with a heat pipe.

There is a classic paper from the US NBS on a micro-degree stirred water
bath which I did cite, along with a more interesting (if less
well-informed) one that relied on the stirrer to provide the heat input
to the water bath.

The VME timing modules use an ECL flop as the clock recovery detector.
It's a bang-bang phase-locked loop with a roughly 1e12 volt/second
slope.

Sounds crude.

The incoming data stream is the clock of the phase detector flop and
the local XO is D. Sorta backwards. Metastability is the prize for
being right.

Even cruder.

Bang-bang PDs are unpopular for some reason.

Switching noise. If you can extract a signal that is smoothly
proportional to the phase difference, you can get a quieter output. You
still have to filter the phase signal you are extracting, and the filter
phase shift can make the control loop unstable if you don't know what
you are doing.

I confess that I don't understand the loop. I don't need to understand things, I just need to make them work.

That's obvious. They'd probably work better if you did understand a bit
more about what you were doing.

I could post the circuit if there were popular demand.

Comic contributions are always welcome.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Saturday, July 18, 2026 08:37:17

On Sun, 19 Jul 2026 01:16:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 8:21 pm, john larkin wrote:

On Sat, 18 Jul 2026 15:26:17 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote:

On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you >>>>>>>>>> proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface >>>>>>> with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30 >>>>>>> centimeters (12 in), while those for high-end applications such as >>>>>>> engineering and land surveying are accurate to within 2 cm (3?4 in) and >>>>>>> can even provide sub-millimeter accuracy with long-term measurement." >>>>>>>
You may not know how they do it, nor be able to do anything that works >>>>>>> quite as well, but while "They don't" may be kind of answer you can >>>>>>> understand it's not one that suggests that you know what you are talking
about.

The discussion was about using a single clock and aligning clock
edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>>>> what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an >>>>>> interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab >>>>> made it perfect clear that the author thought that their gear provided a >>>>> common clock for the entire foot-ball stadium sized lab, with tight
jitter specs much shorter than the propagation time across the facility. >>>>

The hundreds of VME modules are frequency-locked to the master timing
signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic
clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get
there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable. >>>

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly >>>>> isn't serving up the same clock to any of the D-type bistables involved. >>>>

Of course I understand the NIF timing system. I helped design it and
designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have
posted above makes clear. Your VME modules hang off it, rather than
contribute to it.

Well, I helped design the system. It's more interesting than a stirred
water bath.

I've never designed a thermostatted stirred water bath. My 1996 paper
was about Peltier-junction based thermostat. The first version did use >circulating water to take away the waste heat from the Peltier
junctions, but one of colleagues replaced that with a heat pipe.

There is a classic paper from the US NBS on a micro-degree stirred water >bath which I did cite, along with a more interesting (if less
well-informed) one that relied on the stirrer to provide the heat input
to the water bath.

The VME timing modules use an ECL flop as the clock recovery detector.
It's a bang-bang phase-locked loop with a roughly 1e12 volt/second
slope.

Sounds crude.

The incoming data stream is the clock of the phase detector flop and
the local XO is D. Sorta backwards. Metastability is the prize for
being right.

Even cruder.

Bang-bang PDs are unpopular for some reason.

Switching noise. If you can extract a signal that is smoothly
proportional to the phase difference, you can get a quieter output. You >still have to filter the phase signal you are extracting, and the filter >phase shift can make the control loop unstable if you don't know what
you are doing.

I confess that I don't understand the loop. I don't need to understand
things, I just need to make them work.

That's obvious. They'd probably work better if you did understand a bit
more about what you were doing.

There's a long and important list of inventions done by people who
didn't understand how they work. Usually inventions happen and then
the the science takes some time to explain what happened.

Understanding sometimes helps, but demanding understanding severely
restricts possibilities.

Ultimately, we don't understand anything; we just explain some top
levels.

Instinct > experiment > science. Or, even better

Instinct > simulation > product and maybe then some science.

I could post the circuit if there were popular demand.

Comic contributions are always welcome.

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Saturday, July 18, 2026 15:37:14

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113fhu0$3fhs1$1@dont-email.me...

On 7/18/26 03:06, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e92k$34idt$2@dont-email.me...

On 7/17/26 23:35, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113e400$32u9l$1@dont-email.me...

On 7/17/26 19:47, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:113doge$2v1co$2@dont-email.me...

On 7/16/26 20:27, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138k6a$1bsnp$3@dont-email.me...

On 7/15/26 20:05, Edward Rawde wrote:

"Jeroen Belleman" <jeroen@nospam.please> wrote in message news:1138hot$1bsnp$2@dont-email.me...

On 7/15/26 18:18, john larkin wrote:

On Wed, 15 Jul 2026 16:38:57 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Edward Rawde <invalid@invalid.invalid> wrote:

[...]
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

Logic design in the 1960s was a mess, true enough, but aynchronous >>>>>>>>>>> logic need not be. Every flip-flop is in fact a little asynchronous >>>>>>>>>>> state machine. Every logic designer should try his hand at designing
a clocked flip-flop from elementary gates at least once.

An inverter and two SR latches I think.

That's the shoot-from-the-hip approach, which suffers from a race >>>>>>>>> condition. Try again.

Jeroen Belleman

Ok here's divide by 2 in CMOS.
Divide by 3 just needs to duplicate that and add some gating to set up >>>>>>>> next states of 01,10,00 from current states of 00,01,10

Line 451 will need to be unwrapped so that lines 451 and 452
begin with TEXT

Version 4.1

[Deleted...]

That's basically the standard D flip-flop, however, I didn't ask >>>>>>> for a transistor level implementation! The point of the challenge >>>>>>> was to show the use of asynchronous logic at the gate level.

I tried using the nand gates in LTSpice but couldn't get a circuit equivalent to
the one I posted to work. Not sure what I'm doing wrong.
Do you have a working 6-gate edge triggered d-type in LTSpice
using the nand gates under Digital "and" (makes nand or and)?

This here seems to work just fine.

Thanks for that.

It appears that the only difference between the circuit I posted and your circuit
is that adding the 1m ohm resistor to my circuit makes it work.

I wouldn't normally leave inputs open circuit but it doesn't seem to be essential
to connect them or the ground symbols. (Who makes a five-input gate anyway?)

Why is that resistor needed and how would I know where to add a resistor >>>> in other simulations?

Oh, I added that resistor only because you can't give two different
names to the same node. D is effectively connected to nQ.

With the alternate solver the resistor has to be at least 1e-19 ohms.
Any lower than that and you get a 50MHz oscillator instead.

If anyone can explain that to me I'm all ears.

I'd think that for any circuit with sufficient gain and delayed
feedback, there will be some frequency at which it can oscillate.

Rather than specifying Td, try specifying Trise and Tfall, or Tau.
That will reduce the bandwidth and should quench it.

In your schematic, I got it to work with Tau=1n for A1 and A2,
Tau=2n for A4, A5 and A8, and Tau=3n for A3. Curiously, with
Tau=2n for all gates, it still misbehaves. I suppose this is
a good demo of why Spice is a poor logic simulator.

Then again, I wouldn't make a D-flop like that.

Jeroen Belleman

Your divide by 3 circuit works in CMOS but I had to slow things down a bit to get it to simulate.

Version 4.1
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FLAG 3200 -1392 Vdd
FLAG 3664 -1152 C
FLAG 3248 -1040 0
FLAG -1392 -1856 0
FLAG -1424 -2208 Vdd
FLAG -1440 -1808 0
SYMBOL voltage -1744 -1760 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 10n 4n 4n 1m 2m 30)
SYMBOL voltage -1040 -1424 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL pmos4 -592 -2672 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M27
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -304 -2672 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M28
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -496 -2592 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M29
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -496 -2416 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M30
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -592 -2000 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M31
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -304 -2000 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M32
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -496 -1920 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M33
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -496 -1744 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M34
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -592 -1328 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M35
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -304 -1328 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M36
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -496 -1248 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M37
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -496 -1072 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M38
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 192 -592 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M39
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 480 -592 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M40
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 672 -592 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M41
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 288 -512 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M42
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SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 288 -336 R0
WINDOW 0 -46 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M43
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 288 -160 R0
WINDOW 0 -49 25 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M44
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SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 880 -592 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M45
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 880 -512 R0
WINDOW 0 -12 -10 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M46
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -1152 -2000 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M47
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -1152 -1920 R0
WINDOW 0 -12 -10 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M48
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 400 -2272 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M49
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 688 -2272 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M50
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 496 -2192 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M51
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 496 -2016 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M52
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 400 -1600 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M53
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 688 -1600 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M54
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 880 -1600 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M55
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 496 -1520 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M56
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 496 -1344 R0
WINDOW 0 -46 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M57
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 496 -1168 R0
WINDOW 0 -49 25 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M58
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 1264 -2240 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M59
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 1552 -2240 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M60
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 1744 -2240 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M61
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1360 -2160 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M62
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1360 -1984 R0
WINDOW 0 -46 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M63
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 1360 -1808 R0
WINDOW 0 -49 25 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M64
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2176 -2624 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M65
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2464 -2624 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M66
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -2544 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M67
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -2368 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M68
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2176 -1936 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M69
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2464 -1936 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M70
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -1856 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M71
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -1680 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M72
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2176 -1248 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M73
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2464 -1248 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M74
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -1168 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M75
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -992 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M76
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2176 -560 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M77
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2464 -560 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M78
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -480 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M79
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 2272 -304 R0
WINDOW 0 -41 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M80
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 3056 -1184 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M1
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 3344 -1184 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M2
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 3536 -1184 R180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M3
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 3152 -960 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M4
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 3152 -784 R0
WINDOW 0 -46 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M5
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 3152 -608 R0
WINDOW 0 -49 25 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M6
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 2880 -1184 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M7
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 3152 -1104 R0
WINDOW 0 -48 27 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M8
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 -1488 -2000 M180
WINDOW 0 -16 -8 Left 2
WINDOW 3 36 31 Left 2
SYMATTR InstName M9
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 -1488 -1920 R0
WINDOW 0 -12 -10 Left 2
WINDOW 3 62 21 Left 2
SYMATTR InstName M10
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
TEXT -1304 -1360 Left 2 !.tran 0 40m 0
TEXT 1096 -560 Left 2 ;Output A is the 1/3 clock output.
TEXT -1752 -2848 Left 2 ;Asynchronous divide-by-three.
TEXT -1752 -2816 Left 2 ;Jeroen Belleman - 20260717
TEXT -1760 -2632 Left 2 !.MODEL N_1u NMOS LEVEL = 3\n+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 PHI = 0.7 VTO = 0.8 DELTA = 3.0 UO =
650\n+ ETA = 3.0E-6 THETA = 0.1 KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 RSH = 0 NFS = 1E12\n+ TPG = 1 XJ = 500E-9 LD = 100E-9 CGDO =
200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB = 1 MJ = 0.5 CJSW = 300E-12 MJSW = 0.5\n*\n.MODEL P_1u PMOS LEVEL = 3\n+ TOX
= 200E-10 NSUB = 1E17 GAMMA = 0.6 PHI = 0.7 VTO = -0.9 DELTA = 0.1 UO = 250\n+ ETA = 0 THETA = 0.1 KP = 40E-6 VMAX = 5E4 KAPPA
= 1 RSH = 0 NFS = 1E12\n+ TPG = -1 XJ = 500E-9 LD = 100E-9 CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10\n+ CJ = 400E-6 PB = 1 MJ =
0.5 CJSW = 300E-12 MJSW = 0.5
TEXT -1752 -2704 Left 2 ;Models from cmosedu.com
TEXT -1752 -2784 Left 2 ;CMOS conversion by ER

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From joegwinn@3:633/10 to All on Saturday, July 18, 2026 17:57:31

On Sat, 18 Jul 2026 00:30:43 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 7/18/26 00:16, JM wrote:

On Sat, 18 Jul 2026 00:00:45 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

Here's my divide-by-three. There is something fishy though. Note that
I'm not actually using the delay line T1, yet, without it, simulation
fails. Oh well.

Jeroen Belleman

You should really tie unused inputs (and outputs) to gate node 8, that
removes them from the simulation.

Version 4.1

[Deleted...]
I see. It's kind of counter-intuitive though, isn't it?

Yes and no. What matters is what the system matrix generated by all
those deleted lines looks like. Often the result is something
unphysical, which will cause the math to do something strange.

So, the strategy is to suppress everything needless, so it cannot be interpreted strangely. I've seen such things happen in MATLAB for
instance. Also Mathematica. (I don't use SPICE enough to matter.)

Joe

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From JM@3:633/10 to All on Sunday, July 19, 2026 01:51:53

On Fri, 17 Jul 2026 21:06:45 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:

With the alternate solver the resistor has to be at least 1e-19 ohms.
Any lower than that and you get a 50MHz oscillator instead.

If anyone can explain that to me I'm all ears.

There is something odd with your file. I redrew your schematic in
the form I'm more familiar with (see below) and it runs no problem in
about 0.1s on my machine, but for some reason your file behaves
differently.

Version 4.1
SHEET 1 880 680
WIRE -912 -816 -912 -832
WIRE -928 -800 -1200 -800
WIRE -768 -800 -864 -800
WIRE -624 -800 -768 -800
WIRE -928 -768 -1024 -768
WIRE -1024 -704 -1024 -768
WIRE -768 -704 -768 -800
WIRE -1024 -576 -768 -704
WIRE -1024 -576 -1136 -576
WIRE -768 -576 -1024 -704
WIRE -624 -496 -624 -800
WIRE -512 -496 -624 -496
WIRE -1024 -480 -1024 -576
WIRE -944 -480 -1024 -480
WIRE -768 -480 -768 -576
WIRE -768 -480 -880 -480
WIRE -512 -464 -624 -464
WIRE -336 -464 -448 -464
WIRE -288 -464 -336 -464
WIRE -240 -464 -288 -464
WIRE -944 -448 -1024 -448
WIRE -624 -352 -624 -464
WIRE -336 -352 -336 -464
WIRE -1264 -320 -1328 -320
WIRE -1200 -320 -1200 -800
WIRE -1200 -320 -1264 -320
WIRE -1024 -320 -1024 -448
WIRE -752 -320 -1024 -320
WIRE -624 -288 -336 -352
WIRE -336 -288 -624 -352
WIRE -1328 -272 -1328 -320
WIRE -624 -192 -624 -288
WIRE -512 -192 -624 -192
WIRE -1328 -160 -1328 -192
WIRE -512 -160 -624 -160
WIRE -336 -160 -336 -288
WIRE -336 -160 -448 -160
WIRE -1264 -16 -1328 -16
WIRE -912 -16 -1264 -16
WIRE -752 -16 -752 -320
WIRE -752 -16 -848 -16
WIRE -912 16 -1008 16
WIRE -1008 80 -1008 16
WIRE -752 80 -752 -16
WIRE -1008 176 -752 80
WIRE -752 176 -1008 80
WIRE -1008 240 -1008 176
WIRE -912 240 -1008 240
WIRE -752 256 -752 176
WIRE -752 256 -848 256
WIRE -624 256 -624 -160
WIRE -624 256 -752 256
WIRE -608 256 -624 256
WIRE -1136 272 -1136 -576
WIRE -912 272 -1136 272
WIRE -1200 304 -1200 -320
WIRE -912 304 -1200 304
WIRE -1328 448 -1328 -16
WIRE -336 448 -336 -160
WIRE -336 448 -1328 448
FLAG -288 -464 Q
FLAG -1328 -160 0
FLAG -1264 -320 CLK
FLAG -1264 -16 D
SYMBOL Digital\\and -912 -400 M180
WINDOW 3 -37 117 Left 2
SYMATTR Value Td=10n
SYMATTR InstName A8
SYMBOL voltage -1328 -288 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 1m 2m 100)
SYMBOL Digital\\and -896 -720 M180
WINDOW 3 -34 115 Left 2
SYMATTR Value Td=10n
SYMATTR InstName A1
SYMBOL Digital\\and -480 -544 R0
WINDOW 3 -37 117 Left 2
SYMATTR Value Td=10n
SYMATTR InstName A2
SYMBOL Digital\\and -480 -240 R0
WINDOW 3 -37 117 Left 2
SYMATTR Value Td=10n
SYMATTR InstName A3
SYMBOL Digital\\and -880 336 M180
WINDOW 3 -37 117 Left 2
SYMATTR Value Td=10n
SYMATTR InstName A4
SYMBOL Digital\\and -880 64 M180
WINDOW 3 -37 117 Left 2
SYMATTR Value Td=10n
SYMATTR InstName A5
TEXT -1648 72 Left 2 !.tran 0 200m 0

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From JM@3:633/10 to All on Sunday, July 19, 2026 02:00:27

On Sat, 18 Jul 2026 17:57:31 -0400, joegwinn@comcast.net wrote:

I see. It's kind of counter-intuitive though, isn't it?

Yes and no. What matters is what the system matrix generated by all

No, it's bonkers. If anyone sees a nand gate with an input tied to
ground they would quite correctly think the output of the gate is a
logic one. But the authour of LTspice knows better than the rest of
the known universe and does his own thing.

In LTspice if you want a logic zero on an input you either have to
drive it, or tie it to ground with a resistor.

Or you can just attach an unconnected wire to it, or leave it
unconnected, but these two options are undocumented and so really
should not be relied upon.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From JM@3:633/10 to All on Sunday, July 19, 2026 02:10:10

On Sun, 19 Jul 2026 01:51:53 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:

There is something odd with your file. I redrew your schematic in
the form I'm more familiar with (see below) and it runs no problem in
about 0.1s on my machine, but for some reason your file behaves
differently.

Oh - I see in my circuit I have a liitle unconnected wire to node 8 of
A1. That is the difference.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From JM@3:633/10 to All on Sunday, July 19, 2026 03:14:46

On Sun, 19 Jul 2026 02:00:27 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:

On Sat, 18 Jul 2026 17:57:31 -0400, joegwinn@comcast.net wrote:

I see. It's kind of counter-intuitive though, isn't it?

Yes and no. What matters is what the system matrix generated by all

No, it's bonkers. If anyone sees a nand gate with an input tied to
ground they would quite correctly think the output of the gate is a
logic one. But the authour of LTspice knows better than the rest of
the known universe and does his own thing.

In LTspice if you want a logic zero on an input you either have to
drive it, or tie it to ground with a resistor.

Or you can just attach an unconnected wire

(to give a logic zero)

to it, or leave it
unconnected,

(to be clear this removes the input from the netlist and is supposed
to speed up simulation)

but these two options are undocumented and so really
should not be relied upon.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Edward Rawde@3:633/10 to All on Saturday, July 18, 2026 22:35:23

"JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:3s8o5lp10p9r7gmts2d46jtcgjl5h2jttt@4ax.com...

On Sun, 19 Jul 2026 01:51:53 +0100, JM
<sunaecoNoChoppedPork@gmail.com> wrote:

There is something odd with your file. I redrew your schematic in
the form I'm more familiar with (see below) and it runs no problem in
about 0.1s on my machine, but for some reason your file behaves >>differently.

Oh - I see in my circuit I have a liitle unconnected wire to node 8 of
A1. That is the difference.

Yes that works fine here too, with the extra bit of wire.
But you can't put the extra bit of wire on all the gates, only some of them.

I put the circuit into QSpice but haven't so far got further than singular matrix.

And QSpice files don't seem to be ascii so I can't easily post it.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Sunday, July 19, 2026 16:08:35

On 19/07/2026 1:37 am, john larkin wrote:

On Sun, 19 Jul 2026 01:16:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 8:21 pm, john larkin wrote:

On Sat, 18 Jul 2026 15:26:17 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>

wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you >>>>>>>>>>> proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface >>>>>>>> with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30 >>>>>>>> centimeters (12 in), while those for high-end applications such as >>>>>>>> engineering and land surveying are accurate to within 2 cm (3?4 in) and
can even provide sub-millimeter accuracy with long-term measurement." >>>>>>>>
You may not know how they do it, nor be able to do anything that works >>>>>>>> quite as well, but while "They don't" may be kind of answer you can >>>>>>>> understand it's not one that suggests that you know what you are talking
about.

The discussion was about using a single clock and aligning clock >>>>>>> edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>>>>> what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an >>>>>>> interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab >>>>>> made it perfect clear that the author thought that their gear provided a >>>>>> common clock for the entire foot-ball stadium sized lab, with tight >>>>>> jitter specs much shorter than the propagation time across the facility. >>>>>

The hundreds of VME modules are frequency-locked to the master timing >>>>> signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic
clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get >>>> there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable. >>>>

There is actually no explicit clock sent out. The VME clients lock
their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly >>>>>> isn't serving up the same clock to any of the D-type bistables involved. >>>>>

Of course I understand the NIF timing system. I helped design it and >>>>> designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have
posted above makes clear. Your VME modules hang off it, rather than
contribute to it.

Well, I helped design the system. It's more interesting than a stirred
water bath.

I've never designed a thermostatted stirred water bath. My 1996 paper
was about Peltier-junction based thermostat. The first version did use
circulating water to take away the waste heat from the Peltier
junctions, but one of colleagues replaced that with a heat pipe.

There is a classic paper from the US NBS on a micro-degree stirred water
bath which I did cite, along with a more interesting (if less
well-informed) one that relied on the stirrer to provide the heat input
to the water bath.

The VME timing modules use an ECL flop as the clock recovery detector.
It's a bang-bang phase-locked loop with a roughly 1e12 volt/second
slope.

Sounds crude.

The incoming data stream is the clock of the phase detector flop and
the local XO is D. Sorta backwards. Metastability is the prize for
being right.

Even cruder.

Bang-bang PDs are unpopular for some reason.

Switching noise. If you can extract a signal that is smoothly
proportional to the phase difference, you can get a quieter output. You
still have to filter the phase signal you are extracting, and the filter
phase shift can make the control loop unstable if you don't know what
you are doing.

I confess that I don't understand the loop. I don't need to understand
things, I just need to make them work.

That's obvious. They'd probably work better if you did understand a bit
more about what you were doing.

There's a long and important list of inventions done by people who
didn't understand how they work. Usually inventions happen and then
the the science takes some time to explain what happened.

Not that you can list any examples. In reality, new inventions tend to
be patented by several different people at much the same time.

Somebody has published a new way of looking at a problem, and several
people see a way of applying the new insight.

Understanding sometimes helps, but demanding understanding severely
restricts possibilities.

Nobody demands "understanding" but being able to explain what you are
doing to yourself can be very helpful.

Ultimately, we don't understand anything; we just explain some top
levels.

That probably does describe your situation. Atoms and photons are
actually pretty fundamental.

Instinct > experiment > science. Or, even better

Instinct > simulation > product and maybe then some science.

If you can't be bothered to do the science, this can be an attractive delusion.

I could post the circuit if there were popular demand.

Comic contributions are always welcome.

And you have just delivered a whole bunch.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Liz Tuddenham@3:633/10 to All on Sunday, July 19, 2026 08:49:48

john larkin <jl@glen--canyon.com> wrote:

On Tue, 14 Jul 2026 17:48:26 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:

On 7/14/26 02:47, Bill Sloman wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

..

Sometimes you do need to process externally generated triggers, but in
lots of cases you can avoid it if you try hard enough. Marketing hates
asking customers to even try.

you are joking right??

Why have oscilloscopes that use external triggers? That's some idiotic marketing thing again.

It's extremely useful if you are searching in noise for a waveform that
is related to an external frequency, monitoring the modulation of an
A.M. waveform or looking at a delayed signal.

--
~ Liz Tuddenham ~
(Remove the ".invalid"s and add ".co.uk" to reply)
www.poppyrecords.co.uk

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Sunday, July 19, 2026 21:23:25

On 19/07/2026 5:49 pm, Liz Tuddenham wrote:

john larkin <jl@glen--canyon.com> wrote:

On Tue, 14 Jul 2026 17:48:26 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:

On 7/14/26 02:47, Bill Sloman wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

..

Sometimes you do need to process externally generated triggers, but in >>>> lots of cases you can avoid it if you try hard enough. Marketing hates >>>> asking customers to even try.

you are joking right??

Why have oscilloscopes that use external triggers? That's some idiotic
marketing thing again.

It's extremely useful if you are searching in noise for a waveform that
is related to an external frequency, monitoring the modulation of an
A.M. waveform or looking at a delayed signal.

The question was clearly ironic.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Sunday, July 19, 2026 07:00:07

On Sun, 19 Jul 2026 16:08:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 19/07/2026 1:37 am, john larkin wrote:

On Sun, 19 Jul 2026 01:16:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 8:21 pm, john larkin wrote:

On Sat, 18 Jul 2026 15:26:17 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote:

On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 3:32 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>

wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you >>>>>>>>>>>> proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface >>>>>>>>> with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30 >>>>>>>>> centimeters (12 in), while those for high-end applications such as >>>>>>>>> engineering and land surveying are accurate to within 2 cm (3?4 in) and
can even provide sub-millimeter accuracy with long-term measurement." >>>>>>>>>
You may not know how they do it, nor be able to do anything that works
quite as well, but while "They don't" may be kind of answer you can >>>>>>>>> understand it's not one that suggests that you know what you are talking
about.

The discussion was about using a single clock and aligning clock >>>>>>>> edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>>>>>> what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an >>>>>>>> interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab >>>>>>> made it perfect clear that the author thought that their gear provided a
common clock for the entire foot-ball stadium sized lab, with tight >>>>>>> jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing >>>>>> signal, but certainly don't align their logic clocks in time. The
speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic
clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get >>>>> there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable. >>>>>

There is actually no explicit clock sent out. The VME clients lock >>>>>> their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly
isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and >>>>>> designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have >>>>> posted above makes clear. Your VME modules hang off it, rather than
contribute to it.

Well, I helped design the system. It's more interesting than a stirred >>>> water bath.

I've never designed a thermostatted stirred water bath. My 1996 paper
was about Peltier-junction based thermostat. The first version did use
circulating water to take away the waste heat from the Peltier
junctions, but one of colleagues replaced that with a heat pipe.

There is a classic paper from the US NBS on a micro-degree stirred water >>> bath which I did cite, along with a more interesting (if less
well-informed) one that relied on the stirrer to provide the heat input
to the water bath.

The VME timing modules use an ECL flop as the clock recovery detector. >>>> It's a bang-bang phase-locked loop with a roughly 1e12 volt/second
slope.

Sounds crude.

The incoming data stream is the clock of the phase detector flop and
the local XO is D. Sorta backwards. Metastability is the prize for
being right.

Even cruder.

Bang-bang PDs are unpopular for some reason.

Switching noise. If you can extract a signal that is smoothly
proportional to the phase difference, you can get a quieter output. You
still have to filter the phase signal you are extracting, and the filter >>> phase shift can make the control loop unstable if you don't know what
you are doing.

I confess that I don't understand the loop. I don't need to understand >>>> things, I just need to make them work.

That's obvious. They'd probably work better if you did understand a bit
more about what you were doing.

There's a long and important list of inventions done by people who
didn't understand how they work. Usually inventions happen and then
the the science takes some time to explain what happened.

Not that you can list any examples. In reality, new inventions tend to
be patented by several different people at much the same time.

Fire came before chemistry.

The Romans built things by instict and trial-and-error.

Steam engines came before thermodynamics.

The first working airplane was built by a couple of bicycle mechanics.

Pasteur didn't know about viruses.

DeForest never understood how the triode worked.

Superconductivity was discovered by accident.

The bipolar transistor was an accident.

The only invention that I can think of that was inspired by theory is
the laser. And maybe the tunnel diode.

You should name some inventions that derived from science.

Somebody has published a new way of looking at a problem, and several
people see a way of applying the new insight.

Understanding sometimes helps, but demanding understanding severely
restricts possibilities.

Nobody demands "understanding" but being able to explain what you are
doing to yourself can be very helpful.

Ultimately, we don't understand anything; we just explain some top
levels.

That probably does describe your situation. Atoms and photons are
actually pretty fundamental.

But not yet explained. Quarks, strings, stuff.

Instinct > experiment > science. Or, even better

Instinct > simulation > product and maybe then some science.

If you can't be bothered to do the science, this can be an attractive >delusion.

I could post the circuit if there were popular demand.

Comic contributions are always welcome.

And you have just delivered a whole bunch.

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Monday, July 20, 2026 01:00:06

On 20/07/2026 12:00 am, john larkin wrote:

On Sun, 19 Jul 2026 16:08:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 19/07/2026 1:37 am, john larkin wrote:

On Sun, 19 Jul 2026 01:16:10 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 18/07/2026 8:21 pm, john larkin wrote:

On Sat, 18 Jul 2026 15:26:17 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:

On 18/07/2026 3:37 am, john larkin wrote:

On Sat, 18 Jul 2026 02:54:10 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:

On 15/07/2026 3:25 am, john larkin wrote:

On Wed, 15 Jul 2026 02:58:44 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 2:38 am, john larkin wrote:

On Wed, 15 Jul 2026 02:02:46 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 15/07/2026 1:18 am, john larkin wrote:

On Tue, 14 Jul 2026 23:24:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 14/07/2026 9:12 pm, john larkin wrote:

On Tue, 14 Jul 2026 10:47:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 11:36 pm, john larkin wrote:

On Mon, 13 Jul 2026 16:57:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

On 13/07/2026 2:23 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Mon, 13 Jul 2026 13:53:46 +1000, Bill Sloman <bill.sloman@ieee.org>

wrote:

On 13/07/2026 3:32 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Mon, 13 Jul 2026 01:58:49 +1000, Bill Sloman <bill.sloman@ieee.org>

wrote:

On 13/07/2026 1:28 am, john larkin wrote:

<snip>

We work on facilities that are kilometers square. How are you >>>>>>>>>>>>> proposing to align clock edges across them?

The Global Positioning System is rather more extensive than that. How do
you think that they do it?

They don't.

They use timing information to located positions on the earth surface
with an accuracy of better than a metre.

https://en.wikipedia.org/wiki/Global_Positioning_System

"GPS receivers that use the L5 band have much higher accuracy of 30 >>>>>>>>>> centimeters (12 in), while those for high-end applications such as >>>>>>>>>> engineering and land surveying are accurate to within 2 cm (3?4 in) and
can even provide sub-millimeter accuracy with long-term measurement."

You may not know how they do it, nor be able to do anything that works
quite as well, but while "They don't" may be kind of answer you can >>>>>>>>>> understand it's not one that suggests that you know what you are talking
about.

The discussion was about using a single clock and aligning clock >>>>>>>>> edges. GPS can't align clock edges, for many reasons.

None of which you can articulate, because you don't seem to understand >>>>>>>> what is going on.

Having a common zero-skew clock for all D-flops on Earth would be an >>>>>>>>> interesting concept.

And only ignorant lunatic would waste our time mentioning it.

The paper to which you posted a link, about the National Ignition Lab >>>>>>>> made it perfect clear that the author thought that their gear provided a
common clock for the entire foot-ball stadium sized lab, with tight >>>>>>>> jitter specs much shorter than the propagation time across the facility.

The hundreds of VME modules are frequency-locked to the master timing >>>>>>> signal, but certainly don't align their logic clocks in time. The >>>>>>> speed of light prevents that.

For a certain - rather bizazrre - understanding of "aligning logic >>>>>> clocks in time".

The speed of light makes that more difficult, but if you know the
distances between the devices you know long the signal will take to get >>>>>> there, and you can correct for it. In fact people measure the
propagation delays involved and correct for them. They are pretty stable.

There is actually no explicit clock sent out. The VME clients lock >>>>>>> their local clocks by observing the data stream.

A data stream can't be an explicit clock?

You don't seem to be able to understand what this involved. It certainly
isn't serving up the same clock to any of the D-type bistables involved.

Of course I understand the NIF timing system. I helped design it and >>>>>>> designed the VME modules.

https://www.highlandtechnology.com/Product/V880

You clearly don't understand the NIF timing system - as what you have >>>>>> posted above makes clear. Your VME modules hang off it, rather than >>>>>> contribute to it.

Well, I helped design the system. It's more interesting than a stirred >>>>> water bath.

I've never designed a thermostatted stirred water bath. My 1996 paper
was about Peltier-junction based thermostat. The first version did use >>>> circulating water to take away the waste heat from the Peltier
junctions, but one of colleagues replaced that with a heat pipe.

There is a classic paper from the US NBS on a micro-degree stirred water >>>> bath which I did cite, along with a more interesting (if less
well-informed) one that relied on the stirrer to provide the heat input >>>> to the water bath.

The VME timing modules use an ECL flop as the clock recovery detector. >>>>> It's a bang-bang phase-locked loop with a roughly 1e12 volt/second
slope.

Sounds crude.

The incoming data stream is the clock of the phase detector flop and >>>>> the local XO is D. Sorta backwards. Metastability is the prize for
being right.

Even cruder.

Bang-bang PDs are unpopular for some reason.

Switching noise. If you can extract a signal that is smoothly
proportional to the phase difference, you can get a quieter output. You >>>> still have to filter the phase signal you are extracting, and the filter >>>> phase shift can make the control loop unstable if you don't know what
you are doing.

I confess that I don't understand the loop. I don't need to understand >>>>> things, I just need to make them work.

That's obvious. They'd probably work better if you did understand a bit >>>> more about what you were doing.

There's a long and important list of inventions done by people who
didn't understand how they work. Usually inventions happen and then
the the science takes some time to explain what happened.

Not that you can list any examples. In reality, new inventions tend to
be patented by several different people at much the same time.

Fire came before chemistry.

The Romans built things by instinct and trial-and-error.

They did invent quite a bit of math to help the process.

Steam engines came before thermodynamics.

So what?

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Pasteur didn't know about viruses.

And would have done better if he had. Nobody did at that time.

DeForest never understood how the triode worked.

So what? Lots of other people did.

Superconductivity was discovered by accident.

As part of scientific program to get stuff very cold cold and see what
it did when it was very cold.

The bipolar transistor was an accident.

https://www.goodreads.com/quotes/9178-chance-favors-the-prepared-mind

The quote comes from Louis Pasteur "who didn't know about viruses"

The only invention that I can think of that was inspired by theory is
the laser. And maybe the tunnel diode.

And the Josephson junction? You don't know much about science and it
shows. You should know about antibiotics, and plastics.

You should name some inventions that derived from science.

Surperconductivity is the obvious example. Radar is another. Medical ultrasound was science driven. Microscopes are scientific instruments,
and the scanning electron microscope wasn't invented by a tinkerer.

My father's patent on continuous counter-current-cooking to convert
wood-chip into paper pulp was grounded in a whole lot of scientific work
on the kinetics of the process. Johan Richter

https://en.wikipedia.org/wiki/Johan_Richter_(inventor)

had invented the continuous digestor, but had spent had ten years trying
to get it to run counter-current when my father beat him to it. He sent
a signed copy of his history of paper-making to my father (they knew
each other well), with a rather nice handwritten endorsement of that
success. It's gone into the University of Melbourne technology archives.

Somebody has published a new way of looking at a problem, and several
people see a way of applying the new insight.

Understanding sometimes helps, but demanding understanding severely
restricts possibilities.

Nobody demands "understanding" but being able to explain what you are
doing to yourself can be very helpful.

Ultimately, we don't understand anything; we just explain some top
levels.

That probably does describe your situation. Atoms and photons are
actually pretty fundamental.

But not yet explained. Quarks, strings, stuff.

In exactly what way are atoms and photons "unexplained"?
String theory is trying to cobble together a more fundamental
explanation of how the elementary particles and forces fit together, but
you seem to want to ignore the higher-level stuff.

Instinct > experiment > science. Or, even better

Instinct > simulation > product and maybe then some science.

If you can't be bothered to do the science, this can be an attractive
delusion.

I could post the circuit if there were popular demand.

Comic contributions are always welcome.

And you have just delivered a whole bunch.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Liz Tuddenham@3:633/10 to All on Monday, July 20, 2026 11:09:55

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

--
~ Liz Tuddenham ~
(Remove the ".invalid"s and add ".co.uk" to reply)
www.poppyrecords.co.uk

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Gerhard Hoffmann@3:633/10 to All on Monday, July 20, 2026 14:02:10

Am 20.07.26 um 12:09 schrieb Liz Tuddenham:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

If they did, they might have read about Gustav Wei�kopf / Gustave
Whitehead and his powered flight on Aug-14-1901 near Boston.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Phil Hobbs@3:633/10 to All on Monday, July 20, 2026 12:13:46

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 20.07.26 um 12:09 schrieb Liz Tuddenham:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

If they did, they might have read about Gustav Wei�kopf / Gustave
Whitehead and his powered flight on Aug-14-1901 near Boston.

And don?t forget Alexander Graham Polanski, the first telephone Pole.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Monday, July 20, 2026 22:46:56

On 20/07/2026 8:09 pm, Liz Tuddenham wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

More likely newspapers, and news-letters circulated by people interested
in aeronautics. International technical reports tend to be hard to get
hold of even now, while I read "Aviation Week" regularly when young when
I could get at a library that had a subscription.

I've no idea how the Wright brothers kept in touch.

https://en.wikipedia.org/wiki/Lawrence_Hargrave

managed it from Australia, and seems to have influenced people like the
Wright brothers. He apparently influenced Alexander Graham Bell, but
only to make tetrahedral kites.

John Larkin doesn't seem to be conscious of that kind of influence.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Monday, July 20, 2026 08:58:53

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Don@3:633/10 to All on Monday, July 20, 2026 16:16:05

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 20.07.26 um 12:09 schrieb Liz Tuddenham:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

If they did, they might have read about Gustav Wei�kopf / Gustave
Whitehead and his powered flight on Aug-14-1901 near Boston.

Orville knew:

(AI copy and paste)

"The Mythical Whitehead Flight" is an article written by
Orville Wright in 1945. In it, he refutes the claims that
Gustave Whitehead made a powered flight in 1901, which
are based on an article in the Bridgeport Herald of
August 18, 1901. Wright argues that the story was not
taken seriously until it was published in Reader's Digest.
He also notes that the article was written as an eyewitness
report, but there is no evidence that the author was present
at the event. The claims of Whitehead's flights are still
disputed by mainstream historians, who consider them to be
unsubstantiated.

Regardless, tinkering with bicycles is an obsession with me. My many fat
tire bicycle mods include custom fit, superb German fenders and a small
12 VDC battery to power a motorcycle lamp in front. Here's summertime
bliss in motion:

<https://crcomp.net/arts/spintale/>

During the Winter my bike's tricked out with motorcycle handlebar
heaters, handlebar mittens, and studded snow tires. Here's the whole
winterized package:

<https://crcomp.net/bicycle/winterized.png>

My next project is to incorporate a voice-activated ham radio into the
bike. Last week a hang-glider pilot gave a presentation at my ham
radio club meeting. He showed off his Do It Yourself mountain bike
helmet with an embedded avionic headset.
Hang-gliding has come a long way in the past half century. This
particular pilot typically glides at between 10,000' to 16,000' while
wearing a thermo suit to protect against the extreme cold temperatures.
It's now common for hang-glider pilots to travel from coast to coast.

--
73, Don, WD7Q veritas _|_
liberabit | https://www.qsl.net/wd7q vos |

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From ehsjr@3:633/10 to All on Monday, July 20, 2026 12:25:48

On 7/20/2026 12:16 PM, Don wrote:

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 20.07.26 um 12:09 schrieb Liz Tuddenham:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

If they did, they might have read about Gustav Wei�kopf / Gustave
Whitehead and his powered flight on Aug-14-1901 near Boston.

Orville knew:

(AI copy and paste)

"The Mythical Whitehead Flight" is an article written by
Orville Wright in 1945. In it, he refutes the claims that
Gustave Whitehead made a powered flight in 1901, which
are based on an article in the Bridgeport Herald of
August 18, 1901. Wright argues that the story was not
taken seriously until it was published in Reader's Digest.
He also notes that the article was written as an eyewitness
report, but there is no evidence that the author was present
at the event. The claims of Whitehead's flights are still
disputed by mainstream historians, who consider them to be
unsubstantiated.

Regardless, tinkering with bicycles is an obsession with me. My many fat
tire bicycle mods include custom fit, superb German fenders and a small
12 VDC battery to power a motorcycle lamp in front. Here's summertime
bliss in motion:

<https://crcomp.net/arts/spintale/>

During the Winter my bike's tricked out with motorcycle handlebar
heaters, handlebar mittens, and studded snow tires. Here's the whole winterized package:

<https://crcomp.net/bicycle/winterized.png>

Nice!
Ed

<snip>

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Phil Hobbs@3:633/10 to All on Monday, July 20, 2026 16:30:06

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the Wrights used a canard design.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From piglet@3:633/10 to All on Monday, July 20, 2026 16:55:01

Don <g@crcomp.net> wrote:

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 20.07.26 um 12:09 schrieb Liz Tuddenham:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

If they did, they might have read about Gustav Wei�kopf / Gustave
Whitehead and his powered flight on Aug-14-1901 near Boston.

Orville knew:

(AI copy and paste)

"The Mythical Whitehead Flight" is an article written by
Orville Wright in 1945. In it, he refutes the claims that
Gustave Whitehead made a powered flight in 1901, which
are based on an article in the Bridgeport Herald of
August 18, 1901. Wright argues that the story was not
taken seriously until it was published in Reader's Digest.
He also notes that the article was written as an eyewitness
report, but there is no evidence that the author was present
at the event. The claims of Whitehead's flights are still
disputed by mainstream historians, who consider them to be
unsubstantiated.

Regardless, tinkering with bicycles is an obsession with me. My many fat
tire bicycle mods include custom fit, superb German fenders and a small
12 VDC battery to power a motorcycle lamp in front. Here's summertime
bliss in motion:

<https://crcomp.net/arts/spintale/>

During the Winter my bike's tricked out with motorcycle handlebar
heaters, handlebar mittens, and studded snow tires. Here's the whole winterized package:

<https://crcomp.net/bicycle/winterized.png>

My next project is to incorporate a voice-activated ham radio into the
bike. Last week a hang-glider pilot gave a presentation at my ham
radio club meeting. He showed off his Do It Yourself mountain bike
helmet with an embedded avionic headset.
Hang-gliding has come a long way in the past half century. This particular pilot typically glides at between 10,000' to 16,000' while
wearing a thermo suit to protect against the extreme cold temperatures.
It's now common for hang-glider pilots to travel from coast to coast.

--
73, Don, WD7Q veritas _|_
liberabit | https://www.qsl.net/wd7q vos |

Voice activated ham radio is so passe, you should try voice powered ham
radio - Mike Rainey got a QSO by shouting into a microphone powering a flea power transmitter!

--
piglet

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Monday, July 20, 2026 10:11:23

On Mon, 20 Jul 2026 16:30:06 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the >Wrights used a canard design.

Cheers

Phil Hobbs

I think putting the tail in the front was dynamically unstable, so
they practiced a lot to learn how to fly it.

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Bill Sloman@3:633/10 to All on Tuesday, July 21, 2026 03:22:29

On 21/07/2026 1:58 am, john larkin wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

I don't recall that either of them got a Ph.D. It was essentially a
German innovation, and took a while to get adopted outside Germany.

My Ph.D. supervisor got the first Australian Ph.D. in 1948 - before that Australians went off to England, America or Europe to get the degree.

In a lot of respects it is an academic formalisation of the
apprenticeship system - apprentices trained under the supervision of a
master craftsman.

The Wright brothers weren't supervised by anybody, but like anybody
sensible doing new stuff they paid attention to what the competition was
up to.

--
Bill Sloman, Sydney

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Jeroen Belleman@3:633/10 to All on Monday, July 20, 2026 20:29:18

On 7/20/26 19:11, john larkin wrote:

On Mon, 20 Jul 2026 16:30:06 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>>

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the
Wrights used a canard design.

Cheers

Phil Hobbs

I think putting the tail in the front was dynamically unstable, so
they practiced a lot to learn how to fly it.

I don't know if the Wright flyer was dynamically unstable, but having
the tail in the front doesn't necessarily make it so.

Jeroen Belleman

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From joegwinn@3:633/10 to All on Monday, July 20, 2026 16:08:11

On Mon, 20 Jul 2026 20:29:18 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 7/20/26 19:11, john larkin wrote:

On Mon, 20 Jul 2026 16:30:06 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>>>

In an international situation where a lot of people were working on >>>>>> building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the >>> Wrights used a canard design.

Cheers

Phil Hobbs

I think putting the tail in the front was dynamically unstable, so
they practiced a lot to learn how to fly it.

I don't know if the Wright flyer was dynamically unstable, but having
the tail in the front doesn't necessarily make it so.

True.

My father was an aeronautical engineer. As was his father. My
recollection is that the problem was that those planes stalled easily,
and that this is what caused those accidents. The canard in the front
made the airplane pretty much stall proof.

The Gwinn Aircar was designed to be stall-proof as well, so amateur
pilots could operate one in reasonable safety:

.<https://www.check-six.com/Crash_Sites/Gwinn_Aircar-Hawks.htm>

Joe

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Gerhard Hoffmann@3:633/10 to All on Monday, July 20, 2026 22:35:19

Am 20.07.26 um 18:16 schrieb Don:

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 20.07.26 um 12:09 schrieb Liz Tuddenham:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>

In an international situation where a lot of people were working on
building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

If they did, they might have read about Gustav Wei�kopf / Gustave
Whitehead and his powered flight on Aug-14-1901 near Boston.

Orville knew:

(AI copy and paste)

"The Mythical Whitehead Flight" is an article written by
Orville Wright in 1945. In it, he refutes the claims that
Gustave Whitehead made a powered flight in 1901, which
are based on an article in the Bridgeport Herald of
August 18, 1901. Wright argues that the story was not
taken seriously until it was published in Reader's Digest.
He also notes that the article was written as an eyewitness
report, but there is no evidence that the author was present
at the event. The claims of Whitehead's flights are still
disputed by mainstream historians, who consider them to be
unsubstantiated.

Claiming 44 years later that the Reader's Digest reprint was
more widely circulated than the original local newspaper is not
exactly strong evidence of not-having-happened.

He also made a contract with the Smithsonian that they could
keep the Kitty Hawk as long as they told his story.

Hang-gliding has come a long way in the past half century. This particular pilot typically glides at between 10,000' to 16,000' while
wearing a thermo suit to protect against the extreme cold temperatures.
It's now common for hang-glider pilots to travel from coast to coast.

... for small values from coast to coast. The world record is 3009 Km,
and you need sth. like the Andes or the European Alps aligned to your
flight path, and enough wind from the right direction to produce waves.

Much more won't be possible. You are limited by the time from dusk till
dawn and flying more than 200 Km/h eats your height quickly.

Gerhard

who gave up on gliders at -7 dioptres and bought a motor bike instead.
But I could not resist the temptation of a paraglider flight in
Nepals in the Anapurna region:
< https://www.flickr.com/photos/137684711@N07/43283123114/in/album-72157662535945536/
>

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Phil Hobbs@3:633/10 to All on Monday, July 20, 2026 21:12:40

john larkin <jl@htigct.com> wrote:

On Mon, 20 Jul 2026 16:30:06 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>>

In an international situation where a lot of people were working on >>>>> building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the
Wrights used a canard design.

Cheers

Phil Hobbs

I think putting the tail in the front was dynamically unstable, so
they practiced a lot to learn how to fly it.

Yeah, but when it stalled it settled reasonably gently, whereas L.?s
crashed hard, nose first.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Don@3:633/10 to All on Monday, July 20, 2026 22:41:41

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 20.07.26 um 18:16 schrieb Don:

<snip>

Hang-gliding has come a long way in the past half century. This
particular pilot typically glides at between 10,000' to 16,000' while
wearing a thermo suit to protect against the extreme cold temperatures.
It's now common for hang-glider pilots to travel from coast to coast.

... for small values from coast to coast. The world record is 3009 Km,
and you need sth. like the Andes or the European Alps aligned to your
flight path, and enough wind from the right direction to produce waves.

Much more won't be possible. You are limited by the time from dusk till
dawn and flying more than 200 Km/h eats your height quickly.

Gerhard

who gave up on gliders at -7 dioptres and bought a motor bike instead.
But I could not resist the temptation of a paraglider flight in
Nepals in the Anapurna region: <https://www.flickr.com/photos/137684711@N07/43283123114/in/album-72157662535945536/>

In the current context coast to coast means Pacific to Atlantic. And not necessarily non-stop. Apparently an e-Lift system of some sort can come
into play. And airplanes are able to optionally tow hang-gliders to
altitude.
The ham hang-glider pilot also spoke about how the prevailing winds parallel to the North face of Casper Mountain make it a poor launch
site. But that didn't stop this guy:

<https://vimeo.com/844367361>

The video says "paragliding." But the ham hang-glider pilot called it "para-kiting."

--
73, Don, WD7Q veritas _|_
liberabit | https://www.qsl.net/wd7q vos |

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Don@3:633/10 to All on Monday, July 20, 2026 23:05:08

piglet <erichpwagner@hotmail.com> wrote:

Don <g@crcomp.net> wrote:

<snip>

My next project is to incorporate a voice-activated ham radio into the
bike. Last week a hang-glider pilot gave a presentation at my ham
radio club meeting. He showed off his Do It Yourself mountain bike
helmet with an embedded avionic headset.
Hang-gliding has come a long way in the past half century. This
particular pilot typically glides at between 10,000' to 16,000' while
wearing a thermo suit to protect against the extreme cold temperatures.
It's now common for hang-glider pilots to travel from coast to coast.

Voice activated ham radio is so passe, you should try voice powered ham
radio - Mike Rainey got a QSO by shouting into a microphone powering a flea power transmitter!

The guys would like that topic. Speaking of flea power...

There's a Whispering Gallery at the Griffin Museum of Science and
Industry in Chicago. The acoustically tuned dishes at opposite ends of
the room enable quiet whispers into one dish to be easily heard at the
other.
The ham hang-glider pilot says his wings create an acoustically
tuned dish. It enables him to hear barking dogs and people talking a
mile below. Conversely, he could scream his lungs out, but the people
below would hear nothing. Unless they pointed a dish in his direction.

--
73, Don, WD7Q veritas _|_
liberabit | https://www.qsl.net/wd7q vos |

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From john larkin@3:633/10 to All on Monday, July 20, 2026 18:06:57

On Mon, 20 Jul 2026 16:08:11 -0400, joegwinn@comcast.net wrote:

On Mon, 20 Jul 2026 20:29:18 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 7/20/26 19:11, john larkin wrote:

On Mon, 20 Jul 2026 16:30:06 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid >>>>> (Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics. >>>>>>>

In an international situation where a lot of people were working on >>>>>>> building flying machines and reporting on each other's projects.

Are you saying the Wright brothers would have read international
technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the >>>> Wrights used a canard design.

Cheers

Phil Hobbs

I think putting the tail in the front was dynamically unstable, so
they practiced a lot to learn how to fly it.

I don't know if the Wright flyer was dynamically unstable, but having
the tail in the front doesn't necessarily make it so.

True.

My father was an aeronautical engineer. As was his father. My
recollection is that the problem was that those planes stalled easily,
and that this is what caused those accidents. The canard in the front
made the airplane pretty much stall proof.

The Gwinn Aircar was designed to be stall-proof as well, so amateur
pilots could operate one in reasonable safety:

.<https://www.check-six.com/Crash_Sites/Gwinn_Aircar-Hawks.htm>

Joe

Small planes are dangerous. I can't imagine the carnage if hundreds of
those Joby things were flying over downtown.

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Liz Tuddenham@3:633/10 to All on Tuesday, July 21, 2026 10:16:09

Don <g@crcomp.net> wrote:

[...]

There's a Whispering Gallery at the Griffin Museum of Science and
Industry in Chicago. The acoustically tuned dishes at opposite ends of
the room enable quiet whispers into one dish to be easily heard at the
other.

Aren't these just reflectors? One of them turns diverging waves from
its focus into parallel waves - the other dish then focusses the beam of parallel waves back onto its own focus.

If they are tuned, what frequency are they tuned to - and why?

--
~ Liz Tuddenham ~
(Remove the ".invalid"s and add ".co.uk" to reply)
www.poppyrecords.co.uk

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From Gerhard Hoffmann@3:633/10 to All on Tuesday, July 21, 2026 11:52:43

Am 21.07.26 um 11:16 schrieb Liz Tuddenham:

Don <g@crcomp.net> wrote:

[...]

There's a Whispering Gallery at the Griffin Museum of Science and
Industry in Chicago. The acoustically tuned dishes at opposite ends of
the room enable quiet whispers into one dish to be easily heard at the
other.

Aren't these just reflectors? One of them turns diverging waves from
its focus into parallel waves - the other dish then focusses the beam of parallel waves back onto its own focus.

If they are tuned, what frequency are they tuned to - and why?

The 2 points that define an ellipse have this property.

I was in the ancient Greek theater in Epidauros. It was kinda
annoying because if you stood in the focal point, every bumble bee
there seemed to hum around your head.

Cheers, Gerhard

--- PyGate Linux v1.5.18
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

From joegwinn@3:633/10 to All on Tuesday, July 21, 2026 12:26:19

On Mon, 20 Jul 2026 18:06:57 -0700, john larkin <jl@glen--canyon.com>
wrote:

On Mon, 20 Jul 2026 16:08:11 -0400, joegwinn@comcast.net wrote:

On Mon, 20 Jul 2026 20:29:18 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 7/20/26 19:11, john larkin wrote:

On Mon, 20 Jul 2026 16:30:06 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

john larkin <jl@glen--canyon.com> wrote:

On Mon, 20 Jul 2026 11:09:55 +0100, liz@poppyrecords.invalid.invalid >>>>>> (Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:

On 20/07/2026 12:00 am, john larkin wrote:

[...]

The first working airplane was built by a couple of bicycle mechanics.

In an international situation where a lot of people were working on >>>>>>>> building flying machines and reporting on each other's projects. >>>>>>>

Are you saying the Wright brothers would have read international >>>>>>> technical reports?

Who was their PhD advisor?

John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics

They knew about Lilienthal and how he got himself killed. That?s why the >>>>> Wrights used a canard design.

Cheers

Phil Hobbs

I think putting the tail in the front was dynamically unstable, so
they practiced a lot to learn how to fly it.

I don't know if the Wright flyer was dynamically unstable, but having
the tail in the front doesn't necessarily make it so.

True.

My father was an aeronautical engineer. As was his father. My >>recollection is that the problem was that those planes stalled easily,
and that this is what caused those accidents. The canard in the front
made the airplane pretty much stall proof.

The Gwinn Aircar was designed to be stall-proof as well, so amateur
pilots could operate one in reasonable safety:

.<https://www.check-six.com/Crash_Sites/Gwinn_Aircar-Hawks.htm>

Joe

Small planes are dangerous. I can't imagine the carnage if hundreds of
those Joby things were flying over downtown.

The arrival of WW2 eliminated the market for such a flying car, and
the Gwinn Aircar crash killed the main investor, so I lost my chance
to be a well-spoiled heir with my name on the building.

But flying is far harder than driving, and being freed from stalls is
nice, but there are still lots of ways to crash.

I think the theory of those Joby things is that the driver will be a
robot, and those robots will talk to one another for coordination.
Basically Tesla self driving with a swarm. Which will eventually work
well enough to be noticeably safer than human pilots.

Joe

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