john larkin <jl@glen--canyon.com>wrote:
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
john larkin <jl@glen--canyon.com>wrote:
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Maybe they meant personal digital cameras...
Plenty of digital cameras for example on Mars landers...
Other space probes...
And Hubble and Webb telescopes.
But it is nice that they follow the mission.
On Mon, 06 Apr 2026 15:25:01 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
john larkin <jl@glen--canyon.com>wrote:
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Maybe they meant personal digital cameras...
Plenty of digital cameras for example on Mars landers...
Other space probes...
And Hubble and Webb telescopes.
But it is nice that they follow the mission.
"Holiday photos."
Why does that thing need a pilot? The crew could be asleep the whole
trip.
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Ask a few random people "What does Digital mean?"
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
--
Bill Sloman, Sydney
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us.
Have you produced a circuit to meet my LED drive specification yet?
There are many reasons why I think you never will.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us.
Have you produced a circuit to meet my LED drive specification yet?
There are many reasons why I think you never will.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far >>>>> into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
Digits are fingers (and toes). It is also the numbers from one to ten, because that's how they were originally counted. Digital
massage means applying pressure with a finger.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us.
I was the lead hardware engineer on an instrument project, and expressed the idea that we should do some of the fast number
crunching in emitter-coupled logic. One of the better digital engineers in the team expressed scepticism and said it might be an
attractive idea, but he'd seen it go wrong quite often. When I said that it had always worked for me his response was that I was
an an analog engineer, which did make sense. The TTL specialists were never happy with terminated transmission lines.
Have you produced a circuit to meet my LED drive specification yet?
There are many reasons why I think you never will.
One or more LED's? That's not a specification. The thread is all about John Larkin being rude about a perfectly simple - if
half-baked - EDN circuit, which he clearly couldn't make sense of.
I shouldn't have chipped in to the extent that I did.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
--
Bill Sloman, Sydney
On Mon, 06 Apr 2026 15:25:01 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
john larkin <jl@glen--canyon.com>wrote:
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Maybe they meant personal digital cameras...
Plenty of digital cameras for example on Mars landers...
Other space probes...
And Hubble and Webb telescopes.
But it is nice that they follow the mission.
"Holiday photos."
Why does that thing need a pilot? The crew could be asleep the whole
trip.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far >>>>>> into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
Digits are fingers (and toes). It is also the numbers from one to ten, because that's how they were originally counted. Digital
massage means applying pressure with a finger.
I'm not sure what you're answering here but I have various search engines at my disposal if I need information I don't already have.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us.
I was the lead hardware engineer on an instrument project, and expressed the idea that we should do some of the fast number
crunching in emitter-coupled logic. One of the better digital engineers in the team expressed scepticism and said it might be an
attractive idea, but he'd seen it go wrong quite often. When I said that it had always worked for me his response was that I was
an an analog engineer, which did make sense. The TTL specialists were never happy with terminated transmission lines.
I can remember a time when I wanted an ECL 22V10 but there wan't one
(more than 30 years ago). It doesn't matter if there is now.
john larkin <jl@glen--canyon.com>wrote:
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far
into space."
Maybe they meant personal digital cameras...
Plenty of digital cameras for example on Mars landers...
Other space probes...
And Hubble and Webb telescopes.
But it is nice that they follow the mission.
brian <nospam@b-howie.co.uk>wrote:
In message <10r0j8e$26mpq$1@dont-email.me>, Jan Panteltje ><alien@comet.invalid> writes
john larkin <jl@glen--canyon.com>wrote:
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far >>>into space."
Maybe they meant personal digital cameras...
Plenty of digital cameras for example on Mars landers...
Other space probes...
And Hubble and Webb telescopes.
But it is nice that they follow the mission.
They'll be out of range of the cell-phone networks for uploading to >Facebook or Instagram. The 2 sec delay might screw up the protocol
anyway.
< >Https://www.chron.com/culture/article/artemis-iphones-internet-communications-22191351.php>
Brian
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far >>>>>> into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
Digits are fingers (and toes). It is also the numbers from one to ten, because that's how they were originally counted. Digital
massage means applying pressure with a finger.
I'm not sure what you're answering here but I have various search engines at >my disposal if I need information I don't already have.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us.
I was the lead hardware engineer on an instrument project, and expressed the idea that we should do some of the fast number
crunching in emitter-coupled logic. One of the better digital engineers in the team expressed scepticism and said it might be an
attractive idea, but he'd seen it go wrong quite often. When I said that it had always worked for me his response was that I was
an an analog engineer, which did make sense. The TTL specialists were never happy with terminated transmission lines.
I can remember a time when I wanted an ECL 22V10 but there wan't one
(more than 30 years ago) it doesn't matter if there is now.
Have you produced a circuit to meet my LED drive specification yet?
There are many reasons why I think you never will.
One or more LED's? That's not a specification. The thread is all about John Larkin being rude about a perfectly simple - if
half-baked - EDN circuit, which he clearly couldn't make sense of.
I shouldn't have chipped in to the extent that I did.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
--
Bill Sloman, Sydney
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far >>>>>>> into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
Digits are fingers (and toes). It is also the numbers from one to ten, because that's how they were originally counted. Digital
massage means applying pressure with a finger.
I'm not sure what you're answering here but I have various search engines at >> my disposal if I need information I don't already have.
If you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us.
I was the lead hardware engineer on an instrument project, and expressed the idea that we should do some of the fast number
crunching in emitter-coupled logic. One of the better digital engineers in the team expressed scepticism and said it might be an
attractive idea, but he'd seen it go wrong quite often. When I said that it had always worked for me his response was that I was
an an analog engineer, which did make sense. The TTL specialists were never happy with terminated transmission lines.
I can remember a time when I wanted an ECL 22V10 but there wan't one
(more than 30 years ago) it doesn't matter if there is now.
Have you produced a circuit to meet my LED drive specification yet?
There are many reasons why I think you never will.
One or more LED's? That's not a specification. The thread is all about John Larkin being rude about a perfectly simple - if
half-baked - EDN circuit, which he clearly couldn't make sense of.
I shouldn't have chipped in to the extent that I did.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
--
Bill Sloman, Sydney
There are $5 FPGAs now with 10 ns pin-pin delays, 3000 logic blocks, 1
ns rise/fall, PLLs, cmos and LVDS levels. The internal logic is almost
zero delay.
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
https://www.bbc.com/news/articles/clye6j0g840o
"This is the first time that digital cameras have been taken this far >>>>>>>> into space."
Ask a few random people "What does Digital mean?"
They will tell you - correctly - that it pertains to fingers.
Digits are fingers (and toes). It is also the numbers from one to ten, because that's how they were originally counted. Digital
massage means applying pressure with a finger.
I'm not sure what you're answering here but I have various search engines at
my disposal if I need information I don't already have.
I was the lead hardware engineer on an instrument project, and expressed the idea that we should do some of the fast numberIf you asked them about digital electronics you might get a more sensible answer.
These days hardware electronics is split between analog, digital and mixed signal.
Analog electronic engineers can mostly handle digital and mixed signal electronics, and some of them can do better with fast
digital electronics than regular digital electronic engieers.
No doubt you are one of the better ones or you wouldn't be telling us. >>>>
crunching in emitter-coupled logic. One of the better digital engineers in the team expressed scepticism and said it might be an
attractive idea, but he'd seen it go wrong quite often. When I said that it had always worked for me his response was that I was
an an analog engineer, which did make sense. The TTL specialists were never happy with terminated transmission lines.
I can remember a time when I wanted an ECL 22V10 but there wan't one
(more than 30 years ago) it doesn't matter if there is now.
Have you produced a circuit to meet my LED drive specification yet?
There are many reasons why I think you never will.
One or more LED's? That's not a specification. The thread is all about John Larkin being rude about a perfectly simple - if
half-baked - EDN circuit, which he clearly couldn't make sense of.
I shouldn't have chipped in to the extent that I did.
The number of different responses will be similar to the number of different responses
to a question such as "What does God mean or what does God do?"
Not really. Most people are totally ignorant about electronics, while the religious proselytise furiously.
--
Bill Sloman, Sydney
There are $5 FPGAs now with 10 ns pin-pin delays, 3000 logic blocks, 1
ns rise/fall, PLLs, cmos and LVDS levels. The internal logic is almost
zero delay.
"Almost zero" isn't a lot of help.
Identifying the source of these $5 FPGAs would also be helpful, if you
were posting to to be helpful as opposed to posting to make yourself
look as if you might be competent.
Google says that Microchip IGLOO2/SmartFusion2, Microchip ProASIC3
(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6 parts will do it.
The Microchip ProASIC3 A3P1000 seems to be in that price bracket.
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
There are $5 FPGAs now with 10 ns pin-pin delays, 3000 logic blocks, 1
ns rise/fall, PLLs, cmos and LVDS levels. The internal logic is almost
zero delay.
"Almost zero" isn't a lot of help.
Of course it is, if you actually design stuff. The clbs in an Efinix
chip are 4-input LUTs, so you can do any weird 4-input logic function
with the same near-zero delay. I tested that on a proto board; adding
some logic doesn't noticably affect pin-pin delay. The delay seems to
be dominated by io cells.
I just added an extra-cost feature to a pulse generator box, based on
the behavior of the 4-input LUTs.
Identifying the source of these $5 FPGAs would also be helpful, if you
were posting to to be helpful as opposed to posting to make yourself
look as if you might be competent.
Try digikey for efinix chips. Lots of them.
Google says that Microchip IGLOO2/SmartFusion2, Microchip ProASIC3
(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6 parts will do it.
The Microchip ProASIC3 A3P1000 seems to be in that price bracket.
Yes, there are lots of cheap FPGAs around. Which do you use?
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
There are $5 FPGAs now with 10 ns pin-pin delays, 3000 logic blocks, 1 >>>> ns rise/fall, PLLs, cmos and LVDS levels. The internal logic is almost >>>> zero delay.
"Almost zero" isn't a lot of help.
Of course it is, if you actually design stuff. The clbs in an Efinix
chip are 4-input LUTs, so you can do any weird 4-input logic function
with the same near-zero delay. I tested that on a proto board; adding
some logic doesn't noticably affect pin-pin delay. The delay seems to
be dominated by io cells.
By "almost zero" you mean that you can't measure it, and can't be
bothered to make any kind of quantitative estimate
I just added an extra-cost feature to a pulse generator box, based on
the behavior of the 4-input LUTs.
Of course you have. An extra-performance feature might induce people to
pay the extra cost, if you could quantify the improvement.
Identifying the source of these $5 FPGAs would also be helpful, if you
were posting to to be helpful as opposed to posting to make yourself
look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Google says that Microchip IGLOO2/SmartFusion2, Microchip ProASIC3
(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6 parts will do it.
The Microchip ProASIC3 A3P1000 seems to be in that price bracket.
Yes, there are lots of cheap FPGAs around. Which do you use?
None of them. In the exceedingly unlikely event of my getting a job I'd >start looking, but my colleagues would probably tell me what they used.
In the bad old day, the software to program the parts cost money, so you >tried to use parts that other people had used.
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
Identifying the source of these $5 FPGAs would also be helpful, if you >>>> were posting to to be helpful as opposed to posting to make yourself
look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Google says that Microchip IGLOO2/SmartFusion2, Microchip ProASIC3
(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6 parts will do it.
The Microchip ProASIC3 A3P1000 seems to be in that price bracket.
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you >>>>> were posting to to be helpful as opposed to posting to make yourself >>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2, >Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6 >parts"listed below, that's a singularly stupid assertion, even for you.
I could have done the same exercise on the efinix range, using the same >search string "pin-to-pin delays less than 10nsec" but since the first >search didn't pick up the efinix chips, it would have been a waste of time.
You claim to be using efinix chips that do do that well, so why not tell
us which ones are that good?
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you >>>>>> were posting to to be helpful as opposed to posting to make yourself >>>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2,
Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6
parts"listed below, that's a singularly stupid assertion, even for you.
I could have done the same exercise on the efinix range, using the same
search string "pin-to-pin delays less than 10nsec" but since the first
search didn't pick up the efinix chips, it would have been a waste of time. >>
You claim to be using efinix chips that do do that well, so why not tell
us which ones are that good?
I just named (and you snipped) the T20 and my proto board shows it in
plain sight.
We're going to use the T120 in a new design, because it has so much
dual-port sram and a nice DDR DRAM interface. We think it may be a bit
slower than the T20 as far as logic goes.
If I had an assortment of Efinix chips, I could xray them, and see how
many are bond-outs of the same silicon. I'd suspect that bigger chips
might have slower pin-pin delays.
That's the bummer about FPGAs: the internals keep getting faster but
the i/o cells don't.
Am 08.04.26 um 19:55 schrieb john larkin:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you >>>>>>> were posting to to be helpful as opposed to posting to make yourself >>>>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2,
Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6
parts"listed below, that's a singularly stupid assertion, even for you.
I could have done the same exercise on the efinix range, using the same
search string "pin-to-pin delays less than 10nsec" but since the first
search didn't pick up the efinix chips, it would have been a waste of time. >>>
You claim to be using efinix chips that do do that well, so why not tell >>> us which ones are that good?
I just named (and you snipped) the T20 and my proto board shows it in
plain sight.
We're going to use the T120 in a new design, because it has so much
dual-port sram and a nice DDR DRAM interface. We think it may be a bit
slower than the T20 as far as logic goes.
If I had an assortment of Efinix chips, I could xray them, and see how
many are bond-outs of the same silicon. I'd suspect that bigger chips
might have slower pin-pin delays.
That's the bummer about FPGAs: the internals keep getting faster but
the i/o cells don't.
The I/O cells are intentionally slowed down, esp. for rise/fall time.
Some Xilinx families had options for the I/O cells so you could make
some of them faster. Making them ALL faster was the sure way to
disaster because of ground bounce, esp. when all had the same clock.
I once had a bus fight between a 74AS244 with guaranteed 8*64 mA
outputs and a now museum-grade XC3020. The AS244 said 8*LOW and
the XC3020 wanted 8 * HIGH. The XC3020 won hands-down, even within
valid Voh.
Gerhard
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you >>>>>> were posting to to be helpful as opposed to posting to make yourself >>>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2,
Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6
parts"listed below, that's a singularly stupid assertion, even for you.
I could have done the same exercise on the efinix range, using the same
search string "pin-to-pin delays less than 10nsec" but since the first
search didn't pick up the efinix chips, it would have been a waste of time. >>
You claim to be using efinix chips that do do that well, so why not tell
us which ones are that good?
I just named (and you snipped) the T20 and my proto board shows it in
plain sight.
We're going to use the T120 in a new design, because it has so much
dual-port sram and a nice DDR DRAM interface. We think it may be a bit
slower than the T20 as far as logic goes.
If I had an assortment of Efinix chips, I could xray them, and see how
many are bond-outs of the same silicon. I'd suspect that bigger chips
might have slower pin-pin delays.
That's the bummer about FPGAs: the internals keep getting faster but
the i/o cells don't.
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you >>>>>>> were posting to to be helpful as opposed to posting to make yourself >>>>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2,
Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6
parts"listed below, that's a singularly stupid assertion, even for you.
I could have done the same exercise on the efinix range, using the same
search string "pin-to-pin delays less than 10nsec" but since the first
search didn't pick up the efinix chips, it would have been a waste of time. >>>
You claim to be using efinix chips that do do that well, so why not tell >>> us which ones are that good?
I just named (and you snipped) the T20 and my proto board shows it in
plain sight.
Not plainly enough for me to have been able to read it. And these posts
are supposed to be informative, as opposed to schemes for dispensing clues.
We're going to use the T120 in a new design, because it has so much
dual-port sram and a nice DDR DRAM interface. We think it may be a bit
slower than the T20 as far as logic goes.
If I had an assortment of Efinix chips, I could xray them, and see how
many are bond-outs of the same silicon. I'd suspect that bigger chips
might have slower pin-pin delays.
That's the bummer about FPGAs: the internals keep getting faster but
the i/o cells don't.
The surface of the board is more extensive and noisier than that the
surface of the chip. You need to drive 50R transmission lines to get
signals around the board. Some of the clock lines inside package may
need some attention too.
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you >>>>>>>> were posting to to be helpful as opposed to posting to make yourself >>>>>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2,
Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6
parts"listed below, that's a singularly stupid assertion, even for you. >>>> I could have done the same exercise on the efinix range, using the same >>>> search string "pin-to-pin delays less than 10nsec" but since the first >>>> search didn't pick up the efinix chips, it would have been a waste of time.
You claim to be using efinix chips that do do that well, so why not tell >>>> us which ones are that good?
I just named (and you snipped) the T20 and my proto board shows it in
plain sight.
Not plainly enough for me to have been able to read it. And these posts
are supposed to be informative, as opposed to schemes for dispensing clues. >>
We're going to use the T120 in a new design, because it has so much
dual-port sram and a nice DDR DRAM interface. We think it may be a bit
slower than the T20 as far as logic goes.
If I had an assortment of Efinix chips, I could xray them, and see how
many are bond-outs of the same silicon. I'd suspect that bigger chips
might have slower pin-pin delays.
That's the bummer about FPGAs: the internals keep getting faster but
the i/o cells don't.
The surface of the board is more extensive and noisier than that the
surface of the chip. You need to drive 50R transmission lines to get
signals around the board. Some of the clock lines inside package may
need some attention too.
50r terms make no sense for single-ended cmos logic levels between
chips.
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
Identifying the source of these $5 FPGAs would also be helpful, if you
were posting to to be helpful as opposed to posting to make yourself >>>>>>>>> look as if you might be competent.
Try digikey for efinix chips. Lots of them.
But no specific part numbers.
Do you own a web browser? Seems not.
Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2, >>>>> Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6
parts"listed below, that's a singularly stupid assertion, even for you. >>>>> I could have done the same exercise on the efinix range, using the same >>>>> search string "pin-to-pin delays less than 10nsec" but since the first >>>>> search didn't pick up the efinix chips, it would have been a waste of time.
You claim to be using efinix chips that do do that well, so why not tell >>>>> us which ones are that good?
I just named (and you snipped) the T20 and my proto board shows it in
plain sight.
Not plainly enough for me to have been able to read it. And these posts
are supposed to be informative, as opposed to schemes for dispensing clues. >>>
We're going to use the T120 in a new design, because it has so much
dual-port sram and a nice DDR DRAM interface. We think it may be a bit >>>> slower than the T20 as far as logic goes.
If I had an assortment of Efinix chips, I could xray them, and see how >>>> many are bond-outs of the same silicon. I'd suspect that bigger chips
might have slower pin-pin delays.
That's the bummer about FPGAs: the internals keep getting faster but
the i/o cells don't.
The surface of the board is more extensive and noisier than that the
surface of the chip. You need to drive 50R transmission lines to get
signals around the board. Some of the clock lines inside package may
need some attention too.
50r terms make no sense for single-ended cmos logic levels between
chips.
You don't have a lot of choice if you want to use non-dispersive buried >strip-line to move signals around a printed circuit board.
Trying to get a higher impedance trace means either a very narrow trace
or relatively thick and low dielectric constant layers to sandwich the >trace.
The signals covers about 20cm in one nanosecond, so with sub-nanosecond >signals you can't go far before the reflection from an unterminated line >become embarrassing.
You don't actually want to use CMOS logic levels on that kind of >transmission line. ECL deliberately chose a smaller voltage swing to
keep the current levels tolerable.
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling
took the idea a bit further. I'd be surprised if your efinix chips
didn't offer LVDS drivers. The efinix website says that some of their
parts do.
I did specify LVDS signals for the backplane of a fancy timing unit I
worked on in the 1990s. It never got built - the academic customer ran
out of funding after we'd got the circuit diagrams sorted out, and were >running into the dire printed circuit layout tools that the Radboud >University had foisted on us. I'd done quite well with software we'd had
up to that point, but some Orcad rep had got at the adminstration at
just the wrong moment.
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>> wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
50r terms make no sense for single-ended cmos logic levels between
chips.
You don't have a lot of choice if you want to use non-dispersive buried
strip-line to move signals around a printed circuit board.
Trying to get a higher impedance trace means either a very narrow trace
or relatively thick and low dielectric constant layers to sandwich the
trace.
The signals covers about 20cm in one nanosecond, so with sub-nanosecond
signals you can't go far before the reflection from an unterminated line
become embarrassing.
You don't actually want to use CMOS logic levels on that kind of
transmission line. ECL deliberately chose a smaller voltage swing to
keep the current levels tolerable.
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling
took the idea a bit further. I'd be surprised if your efinix chips
didn't offer LVDS drivers. The efinix website says that some of their
parts do.
I did specify LVDS signals for the backplane of a fancy timing unit I
worked on in the 1990s. It never got built - the academic customer ran
out of funding after we'd got the circuit diagrams sorted out, and were
running into the dire printed circuit layout tools that the Radboud
University had foisted on us. I'd done quite well with software we'd had
up to that point, but some Orcad rep had got at the adminstration at
just the wrong moment.
Pity. Failures are discouraging.
LVDS makes sense sometimes, but not in this case. It takes twice as
many FPGA balls, twice as many ribbon cable wires, and forces the PCB
to have more layers (to route out the BGA) which is expensive and
makes the dielectrics even thinner.
The 6-layer board with single-ended 75 ohm traces will work fine.
The two outer rows of a 0.8mm BGA can be routed out on layer 1, with 5
mil traces. But every row after that needs microvias and another PCB
layer. And each row going in has fewer i/o pins. That's an exponential catastrophe.
Real life poses interesting problems.
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
50r terms make no sense for single-ended cmos logic levels between
chips.
You don't have a lot of choice if you want to use non-dispersive buried
strip-line to move signals around a printed circuit board.
Trying to get a higher impedance trace means either a very narrow trace
or relatively thick and low dielectric constant layers to sandwich the
trace.
The signals covers about 20cm in one nanosecond, so with sub-nanosecond
signals you can't go far before the reflection from an unterminated line >>> become embarrassing.
You don't actually want to use CMOS logic levels on that kind of
transmission line. ECL deliberately chose a smaller voltage swing to
keep the current levels tolerable.
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling
took the idea a bit further. I'd be surprised if your efinix chips
didn't offer LVDS drivers. The efinix website says that some of their
parts do.
I did specify LVDS signals for the backplane of a fancy timing unit I
worked on in the 1990s. It never got built - the academic customer ran
out of funding after we'd got the circuit diagrams sorted out, and were
running into the dire printed circuit layout tools that the Radboud
University had foisted on us. I'd done quite well with software we'd had >>> up to that point, but some Orcad rep had got at the adminstration at
just the wrong moment.
Pity. Failures are discouraging.
LVDS makes sense sometimes, but not in this case. It takes twice as
many FPGA balls, twice as many ribbon cable wires, and forces the PCB
to have more layers (to route out the BGA) which is expensive and
makes the dielectrics even thinner.
The 6-layer board with single-ended 75 ohm traces will work fine.
Yuck.
The two outer rows of a 0.8mm BGA can be routed out on layer 1, with 5
mil traces. But every row after that needs microvias and another PCB
layer. And each row going in has fewer i/o pins. That's an exponential
catastrophe.
Real life poses interesting problems.
Why the insistence ball grid arrays? The T20 is available in 100-pin and >144-pin LQFP packages which are a great deal easier to route. Only the >timing outputs and clocks need to be fast - the data I/O can be
multiplexed or even serial.
It's elegant to fit all the logic into one package, but if splitting it
over a couple of packages makes the routing easier and lets you get away >with fewer layers it may be worth thinking about.
And ribbon cables aren't particularly wonderful transmission lines.
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>> wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
50r terms make no sense for single-ended cmos logic levels between
chips.
You don't have a lot of choice if you want to use non-dispersive buried >>>> strip-line to move signals around a printed circuit board.
Trying to get a higher impedance trace means either a very narrow trace >>>> or relatively thick and low dielectric constant layers to sandwich the >>>> trace.
The signals covers about 20cm in one nanosecond, so with sub-nanosecond >>>> signals you can't go far before the reflection from an unterminated line >>>> become embarrassing.
You don't actually want to use CMOS logic levels on that kind of
transmission line. ECL deliberately chose a smaller voltage swing to
keep the current levels tolerable.
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling
took the idea a bit further. I'd be surprised if your efinix chips
didn't offer LVDS drivers. The efinix website says that some of their
parts do.
I did specify LVDS signals for the backplane of a fancy timing unit I
worked on in the 1990s. It never got built - the academic customer ran >>>> out of funding after we'd got the circuit diagrams sorted out, and were >>>> running into the dire printed circuit layout tools that the Radboud
University had foisted on us. I'd done quite well with software we'd had >>>> up to that point, but some Orcad rep had got at the adminstration at
just the wrong moment.
Pity. Failures are discouraging.
LVDS makes sense sometimes, but not in this case. It takes twice as
many FPGA balls, twice as many ribbon cable wires, and forces the PCB
to have more layers (to route out the BGA) which is expensive and
makes the dielectrics even thinner.
The 6-layer board with single-ended 75 ohm traces will work fine.
Yuck.
You dislike success?
The two outer rows of a 0.8mm BGA can be routed out on layer 1, with 5
mil traces. But every row after that needs microvias and another PCB
layer. And each row going in has fewer i/o pins. That's an exponential
catastrophe.
Real life poses interesting problems.
Why the insistence ball grid arrays? The T20 is available in 100-pin and
144-pin LQFP packages which are a great deal easier to route. Only the
timing outputs and clocks need to be fast - the data I/O can be
multiplexed or even serial.
BGAs are small and have near zero lead inductance. And believe it or
not, they solder better.
I can't multiplex fast pulses with picosecond jitters specified.
Our FPGA configuration and runtime data i/o are already a shared SPI interface from the RP2040 CPU.
It's elegant to fit all the logic into one package, but if splitting it
over a couple of packages makes the routing easier and lets you get away
with fewer layers it may be worth thinking about.
FPGA-internal routings are small and fast.
And ribbon cables aren't particularly wonderful transmission lines.
The fine-pitch one that we are using is great. I alternate the fast
signals with real or effective grounds and get a really clean 75 ohm transmission line.
75 is a convenient impedance for PCB traces and for source termination
in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
50r terms make no sense for single-ended cmos logic levels between >>>>>> chips.
You don't have a lot of choice if you want to use non-dispersive buried >>>>> strip-line to move signals around a printed circuit board.
Trying to get a higher impedance trace means either a very narrow trace >>>>> or relatively thick and low dielectric constant layers to sandwich the >>>>> trace.
The signals covers about 20cm in one nanosecond, so with sub-nanosecond >>>>> signals you can't go far before the reflection from an unterminated line >>>>> become embarrassing.
You don't actually want to use CMOS logic levels on that kind of
transmission line. ECL deliberately chose a smaller voltage swing to >>>>> keep the current levels tolerable.
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling
took the idea a bit further. I'd be surprised if your efinix chips
didn't offer LVDS drivers. The efinix website says that some of their >>>>> parts do.
I did specify LVDS signals for the backplane of a fancy timing unit I >>>>> worked on in the 1990s. It never got built - the academic customer ran >>>>> out of funding after we'd got the circuit diagrams sorted out, and were >>>>> running into the dire printed circuit layout tools that the Radboud
University had foisted on us. I'd done quite well with software we'd had >>>>> up to that point, but some Orcad rep had got at the adminstration at >>>>> just the wrong moment.
Pity. Failures are discouraging.
They aren't enjoyable, but if you make a habit of pushing the boundaries >they do happen, and you can't let them discourage you.
LVDS makes sense sometimes, but not in this case. It takes twice as
many FPGA balls, twice as many ribbon cable wires, and forces the PCB
to have more layers (to route out the BGA) which is expensive and
makes the dielectrics even thinner.
The 6-layer board with single-ended 75 ohm traces will work fine.
Yuck.
You dislike success?
Self-proclaimed success is always somewhat suspect.
The two outer rows of a 0.8mm BGA can be routed out on layer 1, with 5 >>>> mil traces. But every row after that needs microvias and another PCB
layer. And each row going in has fewer i/o pins. That's an exponential >>>> catastrophe.
Real life poses interesting problems.
Why the insistence ball grid arrays? The T20 is available in 100-pin and >>> 144-pin LQFP packages which are a great deal easier to route. Only the
timing outputs and clocks need to be fast - the data I/O can be
multiplexed or even serial.
BGAs are small and have near zero lead inductance. And believe it or
not, they solder better.
Not a lot of help if the points that they get soldered to are hard to >connect to anything else. I'd expect the inner areas pf the ball array
to be devoted to power supply connections for precisely that reason.
I can't multiplex fast pulses with picosecond jitters specified.
What did you thing I meant by "Only the timing outputs and clocks need
to be fast - the data I/O can be multiplexed or even serial"?
Our FPGA configuration and runtime data i/o are already a shared SPI
interface from the RP2040 CPU.
As I was saying they would be.
It's elegant to fit all the logic into one package, but if splitting it
over a couple of packages makes the routing easier and lets you get away >>> with fewer layers it may be worth thinking about.
FPGA-internal routings are small and fast.
Which isn't much help if the external routings aren't.
And ribbon cables aren't particularly wonderful transmission lines.
The fine-pitch one that we are using is great. I alternate the fast
signals with real or effective grounds and get a really clean 75 ohm
transmission line.
That was standard operating practice at Cambridge Instruments in the
late 1980s. I was one of the first to use it in production, but one of
my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond >rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination
in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>> wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
And ribbon cables aren't particularly wonderful transmission lines.
The fine-pitch one that we are using is great. I alternate the fast
signals with real or effective grounds and get a really clean 75 ohm
transmission line.
That was standard operating practice at Cambridge Instruments in the
late 1980s. I was one of the first to use it in production, but one of
my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond
rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination
in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
The inductive glitch is from the loop area at the hand-soldered
transition from the SMA connector into the ribbon cable. That won't
happen on a PCB.
Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz
either, but they are great otherwise, like for 200 ps edges.
The original 3M 50-mil pitch ribbon cable is typically 110 ohms in
this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that
the 25 mil stuff is close to 75 ohms.
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
And ribbon cables aren't particularly wonderful transmission lines.
The fine-pitch one that we are using is great. I alternate the fast
signals with real or effective grounds and get a really clean 75 ohm
transmission line.
That was standard operating practice at Cambridge Instruments in the
late 1980s. I was one of the first to use it in production, but one of
my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond
rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination >>>> in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
The inductive glitch is from the loop area at the hand-soldered
transition from the SMA connector into the ribbon cable. That won't
happen on a PCB.
Really? You may be able to make it tidier, and the loop smaller, but
doing it right might be difficult.
Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz
either, but they are great otherwise, like for 200 ps edges.
For your usual definition of "great" which seems to be "barely good enough".
The original 3M 50-mil pitch ribbon cable is typically 110 ohms in
this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that
the 25 mil stuff is close to 75 ohms.
But not pleased enough to find out the exact value. A google search
threw up 80R and 83R. You probably have nail down the insulator and it's >dielectric constant to get a reliable value.
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>> wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
And ribbon cables aren't particularly wonderful transmission lines. >>>>>The fine-pitch one that we are using is great. I alternate the fast
signals with real or effective grounds and get a really clean 75 ohm >>>>> transmission line.
That was standard operating practice at Cambridge Instruments in the
late 1980s. I was one of the first to use it in production, but one of >>>> my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond >>>> rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination >>>>> in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
The inductive glitch is from the loop area at the hand-soldered
transition from the SMA connector into the ribbon cable. That won't
happen on a PCB.
Really? You may be able to make it tidier, and the loop smaller, but
doing it right might be difficult.
We do stuff like this all the time, and this case isn't a big deal. Of
course it will work first time.
Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz
either, but they are great otherwise, like for 200 ps edges.
For your usual definition of "great" which seems to be "barely good enough".
No, they are great. We did some ATLC e/m simulations to get a good
wideband match to the PCB, to get the pads and stackups right. The fat
center pin isn't ideal but can be corrected for.
https://www.dropbox.com/scl/fi/vfi56wy5hkwva51bx77z6/SS_SMA_Edge.JPG?rlkey=nbmbyb0f54uslcpc0nh7rs21p&raw=1
https://www.dropbox.com/scl/fi/dncsaketsakdormve3i45/Edge_alone_3.jpg?rlkey=13i4pozj116gwk474dc3dnmxt&raw=1
That was interesting. The center pin sims to 100 ohms in free air, not soldered to a board.
The original 3M 50-mil pitch ribbon cable is typically 110 ohms in
this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that
the 25 mil stuff is close to 75 ohms.
But not pleased enough to find out the exact value. A google search
threw up 80R and 83R. You probably have nail down the insulator and it's
dielectric constant to get a reliable value.
Silly me, I just measured the impedance of the cable that we stock. My
old 11802 TDR seems to be pretty good.
Your attitude is that everything that I do is wrong and that you are
always smarter. I gently suggest that you reconsider.
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
And ribbon cables aren't particularly wonderful transmission lines. >>>>>>The fine-pitch one that we are using is great. I alternate the fast >>>>>> signals with real or effective grounds and get a really clean 75 ohm >>>>>> transmission line.
That was standard operating practice at Cambridge Instruments in the >>>>> late 1980s. I was one of the first to use it in production, but one of >>>>> my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond >>>>> rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination >>>>>> in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
The inductive glitch is from the loop area at the hand-soldered
transition from the SMA connector into the ribbon cable. That won't
happen on a PCB.
Really? You may be able to make it tidier, and the loop smaller, but
doing it right might be difficult.
We do stuff like this all the time, and this case isn't a big deal. Of
course it will work first time.
That confession might be held against you. Working right, and working
well enough that the customers don't notice anything wrong, are rather >different levels of performance.
Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz
either, but they are great otherwise, like for 200 ps edges.
For your usual definition of "great" which seems to be "barely good enough".
No, they are great. We did some ATLC e/m simulations to get a good
wideband match to the PCB, to get the pads and stackups right. The fat
center pin isn't ideal but can be corrected for.
https://www.dropbox.com/scl/fi/vfi56wy5hkwva51bx77z6/SS_SMA_Edge.JPG?rlkey=nbmbyb0f54uslcpc0nh7rs21p&raw=1
https://www.dropbox.com/scl/fi/dncsaketsakdormve3i45/Edge_alone_3.jpg?rlkey=13i4pozj116gwk474dc3dnmxt&raw=1
That was interesting. The center pin sims to 100 ohms in free air, not
soldered to a board.
SMA is supposed to be good to 20GHz. A picture of the connector and and
a printout from an electromagnetic field simulation program isn't any
kind of evidence of that kind of performace.
The original 3M 50-mil pitch ribbon cable is typically 110 ohms in
this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that
the 25 mil stuff is close to 75 ohms.
But not pleased enough to find out the exact value. A google search
threw up 80R and 83R. You probably have nail down the insulator and it's >>> dielectric constant to get a reliable value.
Silly me, I just measured the impedance of the cable that we stock. My
old 11802 TDR seems to be pretty good.
"Close to 75 ohms" isn't any kind of exact value.
Your attitude is that everything that I do is wrong and that you are
always smarter. I gently suggest that you reconsider.
Everything you do is a bit slap-dash, and if you were a bit smarter
you'd be able to make it less obvious. Making stuff that is just good
enough to keep your customers happy isn't wrong - it is pretty much >commercial wisdom - but boasting about it isn't a great tactic.
A bit of over-design gives you a solution that will last through a
couple of generations of up-grades and probably save money in the long term.
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
And ribbon cables aren't particularly wonderful transmission lines. >>>>>>>The fine-pitch one that we are using is great. I alternate the fast >>>>>>> signals with real or effective grounds and get a really clean 75 ohm >>>>>>> transmission line.
That was standard operating practice at Cambridge Instruments in the >>>>>> late 1980s. I was one of the first to use it in production, but one of >>>>>> my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond >>>>>> rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination >>>>>>> in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
The inductive glitch is from the loop area at the hand-soldered
transition from the SMA connector into the ribbon cable. That won't
happen on a PCB.
Really? You may be able to make it tidier, and the loop smaller, but
doing it right might be difficult.
We do stuff like this all the time, and this case isn't a big deal. Of
course it will work first time.
That confession might be held against you. Working right, and working
well enough that the customers don't notice anything wrong, are rather
different levels of performance.
As long as we get orders and the checks clear, we are reasonably
happy. Personally, I just want to design stuff.
Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz >>>>> either, but they are great otherwise, like for 200 ps edges.
For your usual definition of "great" which seems to be "barely good enough".
No, they are great. We did some ATLC e/m simulations to get a good
wideband match to the PCB, to get the pads and stackups right. The fat
center pin isn't ideal but can be corrected for.
https://www.dropbox.com/scl/fi/vfi56wy5hkwva51bx77z6/SS_SMA_Edge.JPG?rlkey=nbmbyb0f54uslcpc0nh7rs21p&raw=1
https://www.dropbox.com/scl/fi/dncsaketsakdormve3i45/Edge_alone_3.jpg?rlkey=13i4pozj116gwk474dc3dnmxt&raw=1
That was interesting. The center pin sims to 100 ohms in free air, not
soldered to a board.
SMA is supposed to be good to 20GHz. A picture of the connector and and
a printout from an electromagnetic field simulation program isn't any
kind of evidence of that kind of performace.
We wanted to design the PCB footprint and stackup to best match that connector. I can share it with anyone who's interested.
My humble apologies for annoying you with things that don't interest
you.
The original 3M 50-mil pitch ribbon cable is typically 110 ohms in
this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that >>>>> the 25 mil stuff is close to 75 ohms.
But not pleased enough to find out the exact value. A google search
threw up 80R and 83R. You probably have nail down the insulator and it's >>>> dielectric constant to get a reliable value.
Silly me, I just measured the impedance of the cable that we stock. My
old 11802 TDR seems to be pretty good.
"Close to 75 ohms" isn't any kind of exact value.
Your attitude is that everything that I do is wrong and that you are
always smarter. I gently suggest that you reconsider.
Everything you do is a bit slap-dash, and if you were a bit smarter
you'd be able to make it less obvious. Making stuff that is just good
enough to keep your customers happy isn't wrong - it is pretty much
commercial wisdom - but boasting about it isn't a great tactic.
E/M simulation isn't slap-dash. I followed that up with a little
Dremeling to final-tweak the match.
A bit of over-design gives you a solution that will last through a
couple of generations of up-grades and probably save money in the long term.
How is your business doing?
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
And ribbon cables aren't particularly wonderful transmission lines. >>>>>>>>The fine-pitch one that we are using is great. I alternate the fast >>>>>>>> signals with real or effective grounds and get a really clean 75 ohm >>>>>>>> transmission line.
That was standard operating practice at Cambridge Instruments in the >>>>>>> late 1980s. I was one of the first to use it in production, but one of >>>>>>> my colleagues used in a field fix a little earlier.
Ribbon cable terminations weren't designed to cope with sub-nanosecond >>>>>>> rise-times, so it wasn't all that great.
75 is a convenient impedance for PCB traces and for source termination >>>>>>>> in our FPGA.
https://www.dropbox.com/scl/fi/b9bm19a5u371irmdlas3d/25_mil_rib_TDR.jpg?rlkey=pvz57m7ml42prv4w6hfr10sq6&dl=0
That's a pretty horrible 100% overshoot, if brief.
The inductive glitch is from the loop area at the hand-soldered
transition from the SMA connector into the ribbon cable. That won't >>>>>> happen on a PCB.
Really? You may be able to make it tidier, and the loop smaller, but >>>>> doing it right might be difficult.
We do stuff like this all the time, and this case isn't a big deal. Of >>>> course it will work first time.
That confession might be held against you. Working right, and working
well enough that the customers don't notice anything wrong, are rather
different levels of performance.
As long as we get orders and the checks clear, we are reasonably
happy. Personally, I just want to design stuff.
Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz >>>>>> either, but they are great otherwise, like for 200 ps edges.
For your usual definition of "great" which seems to be "barely good enough".
No, they are great. We did some ATLC e/m simulations to get a good
wideband match to the PCB, to get the pads and stackups right. The fat >>>> center pin isn't ideal but can be corrected for.
https://www.dropbox.com/scl/fi/vfi56wy5hkwva51bx77z6/SS_SMA_Edge.JPG?rlkey=nbmbyb0f54uslcpc0nh7rs21p&raw=1
https://www.dropbox.com/scl/fi/dncsaketsakdormve3i45/Edge_alone_3.jpg?rlkey=13i4pozj116gwk474dc3dnmxt&raw=1
That was interesting. The center pin sims to 100 ohms in free air, not >>>> soldered to a board.
SMA is supposed to be good to 20GHz. A picture of the connector and and
a printout from an electromagnetic field simulation program isn't any
kind of evidence of that kind of performace.
We wanted to design the PCB footprint and stackup to best match that
connector. I can share it with anyone who's interested.
My humble apologies for annoying you with things that don't interest
you.
That's not what you need to apologise for. You should be apologising for >tantalsing us with the output from an electromagnetic field simulation
of half a connector pair, when you should have been simulating the mated >pair of connectors.
The original 3M 50-mil pitch ribbon cable is typically 110 ohms in >>>>>> this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that >>>>>> the 25 mil stuff is close to 75 ohms.
But not pleased enough to find out the exact value. A google search
threw up 80R and 83R. You probably have nail down the insulator and it's >>>>> dielectric constant to get a reliable value.
Silly me, I just measured the impedance of the cable that we stock. My >>>> old 11802 TDR seems to be pretty good.
"Close to 75 ohms" isn't any kind of exact value.
Your attitude is that everything that I do is wrong and that you are
always smarter. I gently suggest that you reconsider.
Everything you do is a bit slap-dash, and if you were a bit smarter
you'd be able to make it less obvious. Making stuff that is just good
enough to keep your customers happy isn't wrong - it is pretty much
commercial wisdom - but boasting about it isn't a great tactic.
E/M simulation isn't slap-dash. I followed that up with a little
Dremeling to final-tweak the match.
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
A bit of over-design gives you a solution that will last through a
couple of generations of up-grades and probably save money in the long term.
How is your business doing?
As you well know, it is totally non-existent.
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
How did you design wideband SMA to PCB edge-launch transitions?
The final tweaks result from real PCBs not being anything like ideal
physics models. Affordable FR4 is a wideband mess.
A bit of over-design gives you a solution that will last through a
couple of generations of up-grades and probably save money in the long term.
How is your business doing?
As you well know, it is totally non-existent.
If you still want to design stuff, get out and meet people. But I
suggest you keep the contempt level not too obvious.
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to
the chief engineer and told him what you had done wrong, so that the knowledge could be passed on?
Instructions are passed down the management chain but management needs
to have information passed back up to them, so they can make informed decisions.
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to
the chief engineer and told him what you had done wrong, so that the knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs
to have information passed back up to them, so they can make informed decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with
the technicians - they loved to gossip.
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and
routed coax cable through a mixed signal 41812 connector. You can put >through mixed signal D-type connectors too. Just to add high end appeal
we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal
physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon clothe
as the top and bottom layers of our six-kayer board and that was back in >1986.
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to
the chief engineer and told him what you had done wrong, so that the
knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs
to have information passed back up to them, so they can make informed
decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more >informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with
the technicians - they loved to gossip.
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
We don't have engineering technicians. We can solder ourselves.
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash - >>>> it is total incompetence. It makes it perfectly obvious why you needed >>>> to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and
routed coax cable through a mixed signal 41812 connector. You can put
through mixed signal D-type connectors too. Just to add high end appeal
we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal
physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth
as the top and bottom layers of our six-kayer board and that was back in
1986.
That might take two months and cost a few hundred times as much.
This isn't bad at all, for a $2 JLC board.
One problem with teflon lams is that the copper adhesion is terrible.
Vias can be flakey too.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
For short traces sending logic levels around, an exotic lam isn't worth it. Even crazy fast PCIe is done on FR4.
Bill Sloman <bill.sloman@ieee.org> wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to
the chief engineer and told him what you had done wrong, so that the
knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs
to have information passed back up to them, so they can make informed
decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more
informative.
Yes, I've never worked anywhere where there were formal channels, the informal one was the coffee break and the canteen and it worked very
well. The Chief Engineer used to wander around the development
department having regular chats with the design engineers to make sure everything was running smoothly and to step in if necessary.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with
the technicians - they loved to gossip.
That's a good plan - and even going out as a locum service engineer from
time to time, so you really get the feel for what they have to contend
with. In one firm I worked for, the designer of a piece of equipment
was on call to the production line and the repair shop if any of his
designs caused them problems.
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash - >>>>> it is total incompetence. It makes it perfectly obvious why you needed >>>>> to Dremel the copper on the board to minimise the impedance mis-match. >>>>
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and
routed coax cable through a mixed signal 41812 connector. You can put
through mixed signal D-type connectors too. Just to add high end appeal
we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal
physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth
as the top and bottom layers of our six-kayer board and that was back in >>> 1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously expensive -
the printed circuit house had had to buy quite a large minimum chunk of
the isocyanate bonded Teflon cloth substrate to make our boards, and
they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible.
Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late >1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the >dielectric constant of the substrate changes along the transmission
line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it. >> Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder.
If you need good performance, you have to take more care.
John Larkin wrote: >|-----------------------------------------------------------------|
|"We don't have engineering technicians. We can solder ourselves."| >|-----------------------------------------------------------------|
All engineers are technicians, as all technicians are engineers, by >definitions.
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)
John Larkin wrote: >|-----------------------------------------------------------------|
|"We don't have engineering technicians. We can solder ourselves."| >|-----------------------------------------------------------------|
All engineers are technicians, as all technicians are engineers, by >definitions.
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)
On Sun, 12 Apr 2026 17:38:43 -0000 (UTC), Niocl?s P?l Caile?n de
Ghloucester <thanks-to@Taf.com> wrote:
John Larkin wrote: >>|-----------------------------------------------------------------|
|"We don't have engineering technicians. We can solder ourselves."| >>|-----------------------------------------------------------------|
All engineers are technicians, as all technicians are engineers, by >>definitions.
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)
Methinks you'll find that the salaries of electronic engineers and >technicians are quite different. From a random AI dust bin of wisdom:
"In California, the average salary for an electronics technician is >approximately $60,000-$66,000 annually ($29-$32 per hour) as of April
2026, with top earners exceeding $80,000-$90,000."
"The average salary for an electronics engineer in the U.S. is
approximately $111,910 to $127,590 per year, according to 2024-2026
data. Top earners can exceed $140,000 annually..."
In other words:
two technicians = one engineer
On Sun, 12 Apr 2026 10:55:02 -0700, Jeff Liebermann <jeffl@cruzio.com>
wrote:
On Sun, 12 Apr 2026 17:38:43 -0000 (UTC), Niocl s P¢l Caile n de
Ghloucester <thanks-to@Taf.com> wrote:
John Larkin wrote:
|-----------------------------------------------------------------|
|"We don't have engineering technicians. We can solder ourselves."|
|-----------------------------------------------------------------|
All engineers are technicians, as all technicians are engineers, by
definitions.
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)
Methinks you'll find that the salaries of electronic engineers and
technicians are quite different. From a random AI dust bin of wisdom:
"In California, the average salary for an electronics technician is
approximately $60,000-$66,000 annually ($29-$32 per hour) as of April
2026, with top earners exceeding $80,000-$90,000."
"The average salary for an electronics engineer in the U.S. is
approximately $111,910 to $127,590 per year, according to 2024-2026
data. Top earners can exceed $140,000 annually..."
In other words:
two technicians = one engineer
People hired as techs very rarely advance to engineering positions.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash - >>>>>> it is total incompetence. It makes it perfectly obvious why you needed >>>>>> to Dremel the copper on the board to minimise the impedance mis-match. >>>>>
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and
routed coax cable through a mixed signal 41812 connector. You can put >>>> through mixed signal D-type connectors too. Just to add high end appeal >>>> we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal >>>>> physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth >>>> as the top and bottom layers of our six-kayer board and that was back in >>>> 1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously expensive -
the printed circuit house had had to buy quite a large minimum chunk of
the isocyanate bonded Teflon cloth substrate to make our boards, and
they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible.
Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late
1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the
dielectric constant of the substrate changes along the transmission
line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it. >>> Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder.
You think the PCIe spec is sloppy?
Use something else in your PC.
If you need good performance, you have to take more care.
Or adaptive equalization.
john larkin <jl@glen--canyon.com> wrote:
On Sun, 12 Apr 2026 10:55:02 -0700, Jeff Liebermann <jeffl@cruzio.com>
wrote:
On Sun, 12 Apr 2026 17:38:43 -0000 (UTC), Niocl?s P?l Caile?n de
Ghloucester <thanks-to@Taf.com> wrote:
John Larkin wrote:
|-----------------------------------------------------------------|
|"We don't have engineering technicians. We can solder ourselves."|
|-----------------------------------------------------------------|
All engineers are technicians, as all technicians are engineers, by
definitions.
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)
Methinks you'll find that the salaries of electronic engineers and
technicians are quite different. From a random AI dust bin of wisdom:
"In California, the average salary for an electronics technician is
approximately $60,000-$66,000 annually ($29-$32 per hour) as of April
2026, with top earners exceeding $80,000-$90,000."
"The average salary for an electronics engineer in the U.S. is
approximately $111,910 to $127,590 per year, according to 2024-2026
data. Top earners can exceed $140,000 annually..."
In other words:
two technicians = one engineer
People hired as techs very rarely advance to engineering positions.
John Larkin
Highland Tech Glen Canyon Design Center
Lunatic Fringe Electronics
Well, apart from Jim Williams of LTC and Errol Dietz, who started out as
Bob Pease?s tech and wound up as CTO of National Semi.
Cheers
Phil Hobbs
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash - >>>>>>> it is total incompetence. It makes it perfectly obvious why you needed >>>>>>> to Dremel the copper on the board to minimise the impedance mis-match. >>>>>>
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and
routed coax cable through a mixed signal 41812 connector. You can put >>>>> through mixed signal D-type connectors too. Just to add high end appeal >>>>> we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal >>>>>> physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth >>>>> as the top and bottom layers of our six-kayer board and that was back in >>>>> 1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously expensive - >>> the printed circuit house had had to buy quite a large minimum chunk of >>> the isocyanate bonded Teflon cloth substrate to make our boards, and
they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible.
Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late
1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the
dielectric constant of the substrate changes along the transmission
line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it.
Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder.
You think the PCIe spec is sloppy?
It's a mass market product, and the production volumes are going to be >higher that 100,000 units per year. You don't seem to design for that
kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions.
Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the
lumps of glass fibre in FR4.
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash - >>>>>>>> it is total incompetence. It makes it perfectly obvious why you needed >>>>>>>> to Dremel the copper on the board to minimise the impedance mis-match. >>>>>>>
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and >>>>>> routed coax cable through a mixed signal 41812 connector. You can put >>>>>> through mixed signal D-type connectors too. Just to add high end appeal >>>>>> we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal >>>>>>> physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth >>>>>> as the top and bottom layers of our six-kayer board and that was back in >>>>>> 1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously expensive - >>>> the printed circuit house had had to buy quite a large minimum chunk of >>>> the isocyanate bonded Teflon cloth substrate to make our boards, and
they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible. >>>>> Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late >>>> 1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the
dielectric constant of the substrate changes along the transmission
line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it.
Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder.
You think the PCIe spec is sloppy?
It's a mass market product, and the production volumes are going to be
higher that 100,000 units per year. You don't seem to design for that
kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions.
Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the
lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
The deconvolution thing is one of the mathematically "ill-posed
problems." Which makes it fun to play with.
I can't see glass weaves in a 20 GHz TDR on a cheap FR4 board.
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to
the chief engineer and told him what you had done wrong, so that the
knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs
to have information passed back up to them, so they can make informed
decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more
informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with
the technicians - they loved to gossip.
We don't have engineering technicians. We can solder ourselves.
Jim and Pease died about the same time.
Pease die in a car accident
Am 12.04.26 um 13:39 schrieb john larkin:
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to >>>> the chief engineer and told him what you had done wrong, so that the
knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs >>>> to have information passed back up to them, so they can make informed
decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more
informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with
the technicians - they loved to gossip.
We don't have engineering technicians. We can solder ourselves.
I was not allowed to solder a single joint in the stuff that
I had designed myself that went to space. Not even moving a wire bridge
from A to B.
Gerhard
Am 13.04.26 um 10:07 schrieb Gerhard Hoffmann:
Pease die in a car accident
Ah, Google knows the incident.
And it was a Beetle, not the small bus.
from there:
< >https://www.edn.com/analog-engineering-legend-bob-pease-killed-in-car-crash/
john larkin <jl@glen--canyon.com>wrote:
On Mon, 13 Apr 2026 09:55:58 +0200, Gerhard Hoffmann <dk4xp@arcor.de>wrote:
Am 12.04.26 um 13:39 schrieb john larkin:
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to >>>>> the chief engineer and told him what you had done wrong, so that the >>>>> knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs >>>>> to have information passed back up to them, so they can make informed >>>>> decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more
informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with >>>> the technicians - they loved to gossip.
We don't have engineering technicians. We can solder ourselves.
I was not allowed to solder a single joint in the stuff that
I had designed myself that went to space. Not even moving a wire bridge >>from A to B.
Gerhard
I visited the DeLaval turbine plant and was not allowed to turn a
trimpot on my own controller. I had to tell a union guy which way to
turn it.
Unions are self-destructive.
john larkin <jl@glen--canyon.com>wrote:
On Mon, 13 Apr 2026 09:55:58 +0200, Gerhard Hoffmann <dk4xp@arcor.de>wrote:
Am 12.04.26 um 13:39 schrieb john larkin:
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to >>>>>> the chief engineer and told him what you had done wrong, so that the >>>>>> knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs >>>>>> to have information passed back up to them, so they can make informed >>>>>> decisions.
If that were the only way information got passed back up to them the >>>>> firm would have foundered very rapidly. In general management doesn't >>>>> want to know and wouldn't have known what it meant if they had been >>>>> told through official channels. Unofficial channels tended to be more >>>>> informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with >>>>> the technicians - they loved to gossip.
We don't have engineering technicians. We can solder ourselves.
I was not allowed to solder a single joint in the stuff that
I had designed myself that went to space. Not even moving a wire bridge
from A to B.
Gerhard
I visited the DeLaval turbine plant and was not allowed to turn a
trimpot on my own controller. I had to tell a union guy which way to
turn it.
I was not allowed to replace a defective capacitor I located in ground equipment in ESA
when they called me to help with trouble shooting.
I said: Look we have that capacitor, can replace it now.
But a whole procedure had to followed.
Seems it was replaced as thing went OK later!
Was a dead short coupling capacitor.
IRC in broadcasting I have cheated by getting parts from the local electronics shop,
things were also often time critical.
We had a large parts store, but not always everything in stock.
But then I also have a paper that says: 'Technician in higher electronics' And an other one 'NERG technician'..
And an other one 'broadcasting engineer'
etc etc
That last one from the exams I did after getting a 6 month training in broadcast equipment, satellite systems, audio, video, studio management, what not
in the school banks .. All payed for by the national network.
Nice trip to Brussels headquarters after passing the exams, then straight to work.
Unions are self-destructive.
No, they protect people.
Gerhard Hoffmann <dk4xp@arcor.de>wrote:
Am 13.04.26 um 11:08 schrieb Jan Panteltje:
john larkin <jl@glen--canyon.com>wrote:
On Mon, 13 Apr 2026 09:55:58 +0200, Gerhard Hoffmann <dk4xp@arcor.de>wrote:
Am 12.04.26 um 13:39 schrieb john larkin:
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to >>>>>>> the chief engineer and told him what you had done wrong, so that the >>>>>>> knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had >>>>>> screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs >>>>>>> to have information passed back up to them, so they can make informed >>>>>>> decisions.
If that were the only way information got passed back up to them the >>>>>> firm would have foundered very rapidly. In general management doesn't >>>>>> want to know and wouldn't have known what it meant if they had been >>>>>> told through official channels. Unofficial channels tended to be more >>>>>> informative.
I did make a habit of talking to the service engineers from time to >>>>>> time, when they were back on-site. I didn't have to make an effort with >>>>>> the technicians - they loved to gossip.
We don't have engineering technicians. We can solder ourselves.
I was not allowed to solder a single joint in the stuff that
I had designed myself that went to space. Not even moving a wire bridge >>> >from A to B.
Gerhard
I visited the DeLaval turbine plant and was not allowed to turn a
trimpot on my own controller. I had to tell a union guy which way to
turn it.
In my case that was not bc of unions. I did not have the annual
exam / paperwork.
I was not allowed to replace a defective capacitor I located in ground equipment in ESA
when they called me to help with trouble shooting.
I said: Look we have that capacitor, can replace it now.
But a whole procedure had to followed.
Seems it was replaced as thing went OK later!
Was a dead short coupling capacitor.
IRC in broadcasting I have cheated by getting parts from the local electronics shop,
things were also often time critical.
We had a large parts store, but not always everything in stock.
But then I also have a paper that says: 'Technician in higher electronics' >> And an other one 'NERG technician'..
And an other one 'broadcasting engineer'
etc etc
That last one from the exams I did after getting a 6 month training in broadcast equipment, satellite systems, audio, video,
studio management, what not
in the school banks .. All payed for by the national network.
Nice trip to Brussels headquarters after passing the exams, then straight to work.
Unions are self-destructive.
No, they protect people.
Sometimes, it goes over the top.
In a previous life, I did sth. for a
huge Berlin based manufacturer of photo typesetters. The engineers
were not allowed to do their circuit drawings in Orcad STD themselves;
that was reserved work for the technical drawing people who knew nothing >about electronics.
They went bust in 1993.
Am 13.04.26 um 04:10 schrieb john larkin:
........
Jim and Pease died about the same time.
Didn't Pease die in a car accident in his VW Bully
on the way home from Jim's funeral?
Even weirder, he had written a publication on how to
avoid car accidents, IIRC.
On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 12/04/2026 9:37 pm, john larkin wrote:You think the PCIe spec is sloppy?
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
We didn't try. We put SMA sockets on the printed circuit board and >>>>>>> routed coax cable through a mixed signal 41812 connector. You can put >>>>>>> through mixed signal D-type connectors too. Just to add high end appeal >>>>>>> we used semi-rigid coaxial cable to link everything together
How did you design wideband SMA to PCB edge-launch transitions? >>>>>>>
The final tweaks result from real PCBs not being anything like ideal >>>>>>>> physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth >>>>>>> as the top and bottom layers of our six-kayer board and that was back in
1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously expensive - >>>>> the printed circuit house had had to buy quite a large minimum chunk of >>>>> the isocyanate bonded Teflon cloth substrate to make our boards, and >>>>> they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible. >>>>>> Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late >>>>> 1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the >>>>> dielectric constant of the substrate changes along the transmission
line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it.
Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder. >>>>
It's a mass market product, and the production volumes are going to be
higher that 100,000 units per year. You don't seem to design for that
kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions.
Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the
lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a
reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Am 13.04.26 um 04:10 schrieb john larkin:
........
Jim and Pease died about the same time.
Didn't Pease die in a car accident in his VW Bully
on the way home from Jim's funeral?
Even weirder, he had written a publication on how to
avoid car accidents, IIRC.
On Mon, 13 Apr 2026 09:55:58 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
Am 12.04.26 um 13:39 schrieb john larkin:
On Sun, 12 Apr 2026 20:22:18 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 5:52 pm, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
...Some of my colleagues screwed up from time
to time, and so did I, but we covered up for one another.
Wouldn't it have been a better-organised firm if you could have gone to >>>>> the chief engineer and told him what you had done wrong, so that the >>>>> knowledge could be passed on?
We didn't need to bother. The technicians always knew when you had
screwed up, and the word got passed around.
Instructions are passed down the management chain but management needs >>>>> to have information passed back up to them, so they can make informed >>>>> decisions.
If that were the only way information got passed back up to them the
firm would have foundered very rapidly. In general management doesn't
want to know and wouldn't have known what it meant if they had been
told through official channels. Unofficial channels tended to be more
informative.
I did make a habit of talking to the service engineers from time to
time, when they were back on-site. I didn't have to make an effort with >>>> the technicians - they loved to gossip.
We don't have engineering technicians. We can solder ourselves.
I was not allowed to solder a single joint in the stuff that
I had designed myself that went to space. Not even moving a wire bridge >>from A to B.
Gerhard
I visited the DeLaval turbine plant and was not allowed to turn a
trimpot on my own controller. I had to tell a union guy which way to
turn it.
Unions are self-destructive.
On Mon, 13 Apr 2026 17:01:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 12/04/2026 9:37 pm, john larkin wrote:You think the PCIe spec is sloppy?
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
We didn't try. We put SMA sockets on the printed circuit board and >>>>>>>> routed coax cable through a mixed signal 41812 connector. You can put >>>>>>>> through mixed signal D-type connectors too. Just to add high end appeal
How did you design wideband SMA to PCB edge-launch transitions? >>>>>>>>
we used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything like ideal >>>>>>>>> physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth >>>>>>>> as the top and bottom layers of our six-kayer board and that was back in
1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously expensive - >>>>>> the printed circuit house had had to buy quite a large minimum chunk of >>>>>> the isocyanate bonded Teflon cloth substrate to make our boards, and >>>>>> they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible. >>>>>>> Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late >>>>>> 1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the >>>>>> dielectric constant of the substrate changes along the transmission >>>>>> line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it.
Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder. >>>>>
It's a mass market product, and the production volumes are going to be >>>> higher that 100,000 units per year. You don't seem to design for that
kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions.
Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the
lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a
reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Here ya go:
https://www.amazon.com/Signals-Systems-Dummies-Mark-Wickert/dp/111847581X
On Mon, 13 Apr 2026 17:01:35 +1000, Bill Sloman <bill.sloman@ieee.org> wrote:<bill.sloman@ieee.org>
On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman
Sloman <bill.sloman@ieee.org>wrote:
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote:
On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote:
On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote:
On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote:
On Thu, 9 Apr 2026 00:00:38 +1000, Bill
Sloman <bill.sloman@ieee.org>wrote:
On 8/04/2026 10:52 pm, john larkin wrote:
On Wed, 8 Apr 2026 16:36:08 +1000, Bill
"Edward Rawde"wrote:
On 8/04/2026 4:39 am, john larkin wrote:
On Mon, 6 Apr 2026 15:23:01 -0400,
wrote in message news:10r10a6$2at4a$2@dont-email.me...<invalid@invalid.invalid> wrote:
"Bill Sloman" <bill.sloman@ieee.org>
wrote in message news:10r0pp5$28hv3$1@dont-email.me...On 7/04/2026 3:32 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org>
wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...On 7/04/2026 2:30 am, Edward Rawde wrote:
"john larkin" <jl@glen--canyon.com>
you needed
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why
can putto Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
How did you design wideband SMA to PCB edge-launch transitions?
We didn't try. We put SMA sockets on the printed circuit board and
routed coax cable through a mixed signal 41812 connector. You
end appealthrough mixed signal D-type connectors too. Just to add high
like idealwe used semi-rigid coaxial cable to link everything together
The final tweaks result from real PCBs not being anything
Teflon clothphysics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded
was back inas the top and bottom layers of our six-kayer board and that
expensive -1986.
That might take two months and cost a few hundred times as much.
It didn't, even in the UK in 1987. The boards were hideously
chunk ofthe printed circuit house had had to buy quite a large minimum
terrible.the isocyanate bonded Teflon cloth substrate to make our boards, and
they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is
the lateVias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in
that the1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means
isn't worth it.dielectric constant of the substrate changes along the transmission
line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam
murder.Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with
You think the PCIe spec is sloppy?
It's a mass market product, and the production volumes are going to be
higher that 100,000 units per year. You don't seem to design for that
kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions.
Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the
lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a
reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Here ya go:
https://www.amazon.com/Signals-Systems-Dummies-Mark-Wickert/dp/111847581X
On 14/04/2026 12:10 am, john larkin wrote:
On Mon, 13 Apr 2026 17:01:35 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 12/04/2026 9:37 pm, john larkin wrote:You think the PCIe spec is sloppy?
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:It didn't, even in the UK in 1987. The boards were hideously expensive -
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
We didn't try. We put SMA sockets on the printed circuit board and >>>>>>>>> routed coax cable through a mixed signal 41812 connector. You can put
How did you design wideband SMA to PCB edge-launch transitions? >>>>>>>>>
through mixed signal D-type connectors too. Just to add high end appeal
we used semi-rigid coaxial cable to link everything together >>>>>>>>>>
The final tweaks result from real PCBs not being anything like ideal >>>>>>>>>> physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth
as the top and bottom layers of our six-kayer board and that was back in
1986.
That might take two months and cost a few hundred times as much. >>>>>>>
the printed circuit house had had to buy quite a large minimum chunk of
the isocyanate bonded Teflon cloth substrate to make our boards, and >>>>>>> they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible. >>>>>>>> Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in the late >>>>>>> 1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the >>>>>>> dielectric constant of the substrate changes along the transmission >>>>>>> line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it.
Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder. >>>>>>
It's a mass market product, and the production volumes are going to be >>>>> higher that 100,000 units per year. You don't seem to design for that >>>>> kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions. >>>>>> Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the >>>>> lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a
reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Here ya go:
https://www.amazon.com/Signals-Systems-Dummies-Mark-Wickert/dp/111847581X
You do seem to be a dummy in this area. I'm not.
The joys of decomposing a complex repetitive signal into it's component >sines - the discrete Fourier transform (or if you do it with the minimum
of arithmetic effort, the fast fourier transform) aren't unknown to me.
Equalisation is just boosting and shifting the components that have been >been attenuated and delayed. If you printed circuit board introduces lot
a of random and frequency dependent little delays it's not easy to find
the correct correction function.
On Tue, 14 Apr 2026 02:53:57 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 14/04/2026 12:10 am, john larkin wrote:
On Mon, 13 Apr 2026 17:01:35 +1000, Bill Sloman <bill.sloman@ieee.org>You do seem to be a dummy in this area. I'm not.
wrote:
On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 12/04/2026 9:37 pm, john larkin wrote:You think the PCIe spec is sloppy?
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman <bill.sloman@ieee.org>It didn't, even in the UK in 1987. The boards were hideously expensive -
wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 11:21 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 2:40 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400, "Edward Rawde"
<invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r10a6$2at4a$2@dont-email.me...
On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:10r0pp5$28hv3$1@dont-email.me...
On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com> wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...
<snip>
The E/M simulation of the un-mated half of a connector isn't slap-dash -
it is total incompetence. It makes it perfectly obvious why you needed
to Dremel the copper on the board to minimise the impedance mis-match.
Right, except that it works.
To your complete satisfaction.
We didn't try. We put SMA sockets on the printed circuit board and >>>>>>>>>> routed coax cable through a mixed signal 41812 connector. You can put
How did you design wideband SMA to PCB edge-launch transitions? >>>>>>>>>>
through mixed signal D-type connectors too. Just to add high end appeal
we used semi-rigid coaxial cable to link everything together >>>>>>>>>>>
The final tweaks result from real PCBs not being anything like ideal
physics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded Teflon cloth
as the top and bottom layers of our six-kayer board and that was back in
1986.
That might take two months and cost a few hundred times as much. >>>>>>>>
the printed circuit house had had to buy quite a large minimum chunk of
the isocyanate bonded Teflon cloth substrate to make our boards, and >>>>>>>> they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is terrible. >>>>>>>>> Vias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency >>>>>>>> substrates, and we used couple of different ones even back in the late >>>>>>>> 1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means that the >>>>>>>> dielectric constant of the substrate changes along the transmission >>>>>>>> line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam isn't worth it.
Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with murder. >>>>>>>
It's a mass market product, and the production volumes are going to be >>>>>> higher that 100,000 units per year. You don't seem to design for that >>>>>> kind of market, and I certainly never did. You can put in a lot of >>>>>> design effort to let you get away with cheapest possible solutions. >>>>>>> Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that. >>>>>>
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the >>>>>> lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a >>>>> reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Here ya go:
https://www.amazon.com/Signals-Systems-Dummies-Mark-Wickert/dp/111847581X >>
The joys of decomposing a complex repetitive signal into it's component
sines - the discrete Fourier transform (or if you do it with the minimum
of arithmetic effort, the fast fourier transform) aren't unknown to me.
Equalisation is just boosting and shifting the components that have been
been attenuated and delayed. If you printed circuit board introduces lot
a of random and frequency dependent little delays it's not easy to find
the correct correction function.
Given signal S and bad comm channel C, the product is ugly signal
S * C.
If you work in frequency domain, S has a complex spectrum and C has a
complex transform and the * above is a complex multiply of the
spectra.
If you work in time domain (as I do) S is a waveform and C is the
impulse response of the channel, and the * operator is convolution.
In either case, we want an equilizer E such that
S * C * E = S
namely C * E = 1
In frequency domain, you do a complex divide to calculate E, which
generally explodes.
In time domain I have an iterative algorithm to get E. Iterate too
many times and it explodes too.
The problem is ill-posed and non-causal, which is what makes it
interesting.
Adaptive equalizer chips can input an unrecognizable hairball and
output a beautiful data stream. Things like fast PCIe wouldn't work
without adaptive equalizers.
On 14/04/2026 12:10 am, john larkin wrote:
On Mon, 13 Apr 2026 17:01:35 +1000, Bill Sloman <bill.sloman@ieee.org> wrote:
<bill.sloman@ieee.org>On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org> >>> wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 11:21 am, john larkin wrote:
On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 2:40 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman
Sloman <bill.sloman@ieee.org>wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill
Sloman <bill.sloman@ieee.org>wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill
"Edward Rawde"wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400,
wrote in message news:10r10a6$2at4a$2@dont-email.me...<invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org>
wrote in message news:10r0pp5$28hv3$1@dont-email.me...On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org>
wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com...On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com>
slap-dash -
<snip>
The E/M simulation of the un-mated half of a connector isn't
you neededit is total incompetence. It makes it perfectly obvious why
mis-match.to Dremel the copper on the board to minimise the impedance
can put
Right, except that it works.
To your complete satisfaction.
We didn't try. We put SMA sockets on the printed circuit board and >>>>>>>> routed coax cable through a mixed signal 41812 connector. You
How did you design wideband SMA to PCB edge-launch transitions? >>>>>>>>
end appealthrough mixed signal D-type connectors too. Just to add high
like idealwe used semi-rigid coaxial cable to link everything together >>>>>>>>>
The final tweaks result from real PCBs not being anything
Teflon clothphysics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded
was back inas the top and bottom layers of our six-kayer board and that
expensive -It didn't, even in the UK in 1987. The boards were hideously1986.
That might take two months and cost a few hundred times as much. >>>>>>
chunk ofthe printed circuit house had had to buy quite a large minimum
terrible.the isocyanate bonded Teflon cloth substrate to make our boards, and >>>>>> they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is
the lateVias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency
substrates, and we used couple of different ones even back in
that the1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means
isn't worth it.dielectric constant of the substrate changes along the transmission >>>>>> line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam
murder.Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with
You think the PCIe spec is sloppy?
It's a mass market product, and the production volumes are going to be >>>> higher that 100,000 units per year. You don't seem to design for that >>>> kind of market, and I certainly never did. You can put in a lot of
design effort to let you get away with cheapest possible solutions. >>>>> Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that.
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the >>>> lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a
reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Here ya go:
https://www.amazon.com/Signals-Systems-Dummies-Mark-Wickert/dp/111847581X
You do seem to be a dummy in this area. I'm not.
The joys of decomposing a complex repetitive signal into it's component >sines waves - the discrete Fourier transform (or if you do it with the >minimum of arithmetic effort, the fast fourier transform) aren't unknown
to me.
Equalisation is just boosting and shifting the components that have been >been attenuated and delayed. If your printed circuit board introduces a
lot a of random and frequency dependent little delays it's not easy to
find the correct correction function.
On Tue, 14 Apr 2026 03:47:59 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 14/04/2026 12:10 am, john larkin wrote:
On Mon, 13 Apr 2026 17:01:35 +1000, Bill Sloman <bill.sloman@ieee.org><bill.sloman@ieee.org>
wrote:
On 13/04/2026 12:19 pm, john larkin wrote:
On Mon, 13 Apr 2026 11:36:45 +1000, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 13/04/2026 1:01 am, john larkin wrote:
On Sun, 12 Apr 2026 23:07:30 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 12/04/2026 9:37 pm, john larkin wrote:
On Sun, 12 Apr 2026 14:49:35 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 12/04/2026 2:53 am, john larkin wrote:
On Sat, 11 Apr 2026 16:02:55 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 11/04/2026 3:55 am, john larkin wrote:
On Sat, 11 Apr 2026 03:05:16 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 11/04/2026 1:13 am, john larkin wrote:
On Sat, 11 Apr 2026 00:06:40 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 7:00 pm, john larkin wrote:
On Fri, 10 Apr 2026 16:51:21 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 11:21 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 03:41:39 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 2:40 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Fri, 10 Apr 2026 01:55:00 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 10/04/2026 1:23 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 16:21:20 +1000, Bill Sloman
<bill.sloman@ieee.org>wrote:
On 9/04/2026 3:55 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 03:20:55 +1000, Bill Sloman
Sloman <bill.sloman@ieee.org>wrote:
On 9/04/2026 2:36 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>> On Thu, 9 Apr 2026 00:00:38 +1000, Bill
Sloman <bill.sloman@ieee.org>wrote:
On 8/04/2026 10:52 pm, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Wed, 8 Apr 2026 16:36:08 +1000, Bill
"Edward Rawde"wrote:
On 8/04/2026 4:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> On Mon, 6 Apr 2026 15:23:01 -0400,
wrote in message news:10r10a6$2at4a$2@dont-email.me... >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> On 7/04/2026 3:32 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org><invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "Bill Sloman" <bill.sloman@ieee.org>
wrote in message news:10r0pp5$28hv3$1@dont-email.me... >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> On 7/04/2026 2:30 am, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> "john larkin" <jl@glen--canyon.com>
wrote in message news:o2i7tk5q0b453cv1ag9jq0ec787n8lu9iu@4ax.com... >>>>>>>>>>
slap-dash -<snip>
The E/M simulation of the un-mated half of a connector isn't
you neededit is total incompetence. It makes it perfectly obvious why
mis-match.to Dremel the copper on the board to minimise the impedance
can put
Right, except that it works.
To your complete satisfaction.
We didn't try. We put SMA sockets on the printed circuit board and >>>>>>>>>> routed coax cable through a mixed signal 41812 connector. You
How did you design wideband SMA to PCB edge-launch transitions? >>>>>>>>>>
end appealthrough mixed signal D-type connectors too. Just to add high
like idealwe used semi-rigid coaxial cable to link everything together >>>>>>>>>>>
The final tweaks result from real PCBs not being anything
Teflon clothphysics models. Affordable FR4 is a wideband mess.
So why use FR4? We put in two layers of isocyanate bonded
was back inas the top and bottom layers of our six-kayer board and that
expensive -It didn't, even in the UK in 1987. The boards were hideously1986.
That might take two months and cost a few hundred times as much. >>>>>>>>
chunk ofthe printed circuit house had had to buy quite a large minimum
terrible.the isocyanate bonded Teflon cloth substrate to make our boards, and >>>>>>>> they got the money back over of a handful of boards
This isn't bad at all, for a $2 JLC board.
<snipped uninformative pictures>
One problem with teflon lams is that the copper adhesion is
the lateVias can be flakey too.
Ours were fine. Nowadays there a whole range of high frequency >>>>>>>> substrates, and we used couple of different ones even back in
that the1980's.
Some of the rigid Isola materials are better,
if you really need a low-loss dielectric.
It's not just the low-loss. The glass-fibre mat in FR4 means
isn't worth it.dielectric constant of the substrate changes along the transmission >>>>>>>> line, and that generate small reflections.
For short traces sending logic levels around, an exotic lam
murder.Even crazy fast PCIe is done on FR4.
Keep the specification sloppy enough and you can get away with
You do seem to be a dummy in this area. I'm not.
You think the PCIe spec is sloppy?
It's a mass market product, and the production volumes are going to be >>>>>> higher that 100,000 units per year. You don't seem to design for that >>>>>> kind of market, and I certainly never did. You can put in a lot of >>>>>> design effort to let you get away with cheapest possible solutions. >>>>>>> Use something else in your PC.
Why would I? It's a cheap mass market product, and it works.
If I needed something better - and could afford it - I'd buy that. >>>>>>
If you need good performance, you have to take more care.
Or adaptive equalization.
Adaptive equalisation won't get rid of the small reflections from the >>>>>> lumps of glass fibre in FR4.
Of course it will.
Given a linearly distorted signal without too much noise, there is a >>>>> reciprocal function that undoes the distortion. It's "the
deconvolution problem" to find that reciprocal function.
Word salad.
Here ya go:
https://www.amazon.com/Signals-Systems-Dummies-Mark-Wickert/dp/111847581X >>
You are universally wonderful.
The joys of decomposing a complex repetitive signal into it's component
sines waves - the discrete Fourier transform (or if you do it with the
minimum of arithmetic effort, the fast fourier transform) aren't unknown
to me.
Equalisation is just boosting and shifting the components that have been
been attenuated and delayed. If your printed circuit board introduces a
lot a of random and frequency dependent little delays it's not easy to
find the correct correction function.
The frequency-domain way to calculate the equalizer is to do a complex
divide of the equivalent FFTs. That tends to blow up with divides by
small numbers or zeroes.
There is a world of academic papers on how to work around the FFT
division crisis, and they turn out to be messy and iterative and
ill-posed too.
As the book says, frequency domain and time domain are just ways to
look at the same things.
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