I am crossposting as a person who reads a different newsgroup might
give a better answer.

Awe74 wrote in comp.arch.fpga - |---------------------------------------------------------------------|
|"Hi, |
| |
|I'm looking for an old VeriBest Design Capture release from 1999. |
| |
|I found this old file list, which contains: |
| | |PWAADP01.ZIP 1,459,067 31/08/99 | |PWAADP02.ZIP |
|.. | |PWAADP28.ZIP |
| |
|ANALOG AND DESIGN CAPTURE V99.0A (C) VERIBEST [XX/28] |
| |
|The files appear to be a 28-part split archive of VeriBest Analog and|
|Design Capture V99.0A. |
| |
|I'm particularly interested in finding the original | |PWAADP01ƒ??PWAADP28 ZIP files, or any archive/tape dump containing |
|them. |
| |
|Does anyone here still have these files, or know where this release | |originally came from (BBS, FTP site, CD, DAT/tape archive, etc.)? |
| |
|I'm also interested in any information about the original file area |
|where these were distributed, possibly under directories such as: |
| |
|/CAD |
|/CAD'S |
|/EDA |
|/PCB |
| |
|The file list I have is dated September 3, 1999, so I'm trying to |
|trace the original source or an archival copy. |
| |
|If you have the files, an old BBS/tape dump, or even just information|
|about where they might have been archived, I'd be very grateful. |
| | |Thanks!" | |---------------------------------------------------------------------|

I do not know them. Rick Filipkiewicz gave me the impression that
Mentor bought VeriBest.

Veribest is referenced in other posts. E.g.

Message-ID: <3C21B975.27968FEB@algor.co.uk>
Date: Thu, 20 Dec 2001 10:12:05 +0000
From: Rick Filipkiewicz <rick@algor.co.uk>
Newsgroups: comp.arch.fpga
Subject: Re: Spartan-IIE schematic symbol?

|--------------------------------------------------------------------------| |"We have a very similar thing for VeriBest (now owned by Mentor) | |schems. In some | |form or another we have been auto-generating schems. from pinout files | |since we | |moved to CPLDs from PALs. |
| | |For the original versions we did use a ``canned'' part placed on a | |primitive | |schem with wires connected to all the part pins and the wires had temp | |names | |related to the parts pin names. | |Then used a tool that came with the schem editor to rename the wires | |that were | |"live" and delete the rest. This auto-schem was hidden in a hierarchy | |block. |
| | |We can now contruct the whole thing from the ground up using schem | |editor's list | |of symbols which includes, for a ViretxE part, 8 ``bank'' symbols, a power| |block, and a configuration block." | |--------------------------------------------------------------------------|

Message-ID: <ullw2e9kl.fsf@trw.com>
Date: Mon, 16 Jun 2003 08:00:10 +0000
From: Martin Thompson <martin.j.thompson@trw.com>
Newsgroups: comp.lang.vhdl
Subject: Re: Veribest Setup

|----------------------------------------------------------------------------| |""Yu. B" <Yub@enel.ucalgary.ca> writes: | | |

Hi, all, |
| I am new to VHDL. I installed the VeriBest VHDL software and loaded up the| dummy .vhd file as listed below: |

| | |First thing... Veribest got bought by Mentor Graphics a long time | |ago. VB VHDL is now no longer being actively developed, but Mentor | |should be alright about transferring your licenses to ModelSim (at | |least they were in our case). | | |

---------------------------------------------------------------------- | ENTITY serial_adder IS |
| END serial_adder; |
| ---------------------------------------------------------------------- |
|

| | |I think that ought to be OK! Not a lot to go wrong... | | |

| However, whenever I tried to compile the file, I got the error message | ---------------------------------------------------------------------- | VeriBest VHDL Compiler - 15.01.00.14 |
|
|
| ------------------- |
| 1: b14^D |
| ^^^ |
| [Failure] Syntax error : received IDENTIFIER |
| while expecting COMMENT |
| or 'architecture' or 'configuration' or 'entity' or 'library' |
| or 'package' or 'use' |
|
| Done |
| ---------------------------------------------------------------------- |
|

| | |Very bizarre - are you using the GUI or the command line? You could | |try using the opposite method and see if that changes things. | | | |Another thought - my newsreader shows a CTRL-D character after the | |b14, I wonder if that has got into your file somehow and confused the | |compiler... | | | |Sorry not to be more help :-( | | | |Martin | | | |-- | |martin.j.thompson@trw.com | |TRW Conekt, Solihull, UK | | http://www.trw.com/conekt" | |----------------------------------------------------------------------------|

Message-ID: <bq7p8t$o0e$1@mira.e-technik.uni-dortmund.de>
Date: Fri, 28 Nov 2003 15:23:09 +0000
From: Edwin Naroska <edwin@ds.e-technik.uni-dortmund.de>
Subject: comp.lang.vhdl FAQ part 3 of 4: products & services

|------------------------------------------------------------------------| |"VeriBest, Incorporated | |USA: | |6101 Lookout Road | |Boulder, Colorado 80301 | |Phone: 303.581.2300 | |Fax: 303.581.9972 | |toll free: 800.VERIBEST | |WWW: http://www.veribest.com | |Email: info@veribest.com | |United Kingdom: | |44.1793.511199 | |Germany: | |49.89.96284.0 | |France: | |33.1.41.76.35.00 | |Nordic: | |46.8.92.54.00 | |Asia/Pacific: | |852.2.893.3621 | |Japan: | |81.3.3797.5277 |
| | |Company: | |VeriBest, Inc. is a broad line supplier of EDA solutions that enable | |companies to solve their critical business issues by doing more and | |spending less. VeriBest pioneered the Windows NT EDA market by | |introducing its VeriBest PCB design solution in 1994 and continues to | |offer the best EDA price/performance available in the industry. |
| | |VHDL Products: | |VeriBest Graphical High-Level Design: VeriBest Graphical High-Level | |Design is a language independent, graphical, state-machine entry and | |debug environment. VBGHLD includes a state table editor, a state diagram| |editor and a state flow graph editor. VBGHLD is integrated with VeriBest| |Design Capture to give you a single environment for your design | |definition needs. VBGHLD outputs both VHDL and Verilog. |
| | |VeriBest VHDL: | |Introduced at DAC '96, VeriBest VHDL is a VHDL 1076-93 compliant | |simulator offering unique debug features such as a Network Traverser. | |VBVHDL is an Windows NT-product and utilizes standard NT ease-of-use | |features such as signal drag-n-drop into the various display and debug | |features. |
| | |VeriBest High-Level Design: | |VeriBest High-Level Design is a VHDL/Verilog synthesis application that | |outputs VHDL and Verilog for post-synthesis simulation and outputs | |data for the VeriBest Design Optimizer." | |------------------------------------------------------------------------|

Message-ID: <hdtfq5lojgq4olokdi5t0edt5k86rr437q@4ax.com>
Date: Mon, 22 Mar 2010 23:27:03 +0000
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Subject: Re: Finally, selling my old Xilinx/Viewlogic software package

|---------------------------------------------------------------------|
|"On Mon, 22 Mar 2010 20:38:42 +0000, Peter wrote: |
| | |>Towards the end of my era of doing complicated logic designs, a very|

nice product was from somebody like Altera. It was a FREE VHDL | |>compiler, crippled to work with just a few low end devices e.g. a | |>22V10. |

| | |Cypress WARP, maybe? I designed a good few PAL/GAL | |devices with it. There was a cut-off-at-the-knees | |version of the Veribest VHDL simulator, too - |
|can't remember who shipped that. I still have a |
|copy on my machine, but I can't get it to run under XP. |
|-- | |Jonathan Bromley" | |---------------------------------------------------------------------|

Message-ID: <ba1d7793.0309180856.2b11c16e@posting.google.com>
Date: Thu, 18 Sep 2003 16:56:52 +0000
From: Michael Dunbar <thedunbars@ntlworld.com>
Newsgroups: comp.arch.fpga
Subject: Re: Actel Desktop Schematic Viewer

|--------------------------------------------------|
|"Andrew Paule <lsboogy@qwest.net> wrote in message| |news:<6E2ab.725$VC1.32489@news.uswest.net>... |

What format are they in? |
|

| |
|Veribest, *.sbk and *.blk files." | |--------------------------------------------------|

Message-ID: <adb3971c.0301122308.370acdbd@posting.google.com>
Date: Mon, 13 Jan 2003 07:08:23 +0000
From: john jakson <johnjakson@yahoo.com>
Newsgroups: comp.arch.fpga
Subject: Re: SChematic design approach compared to VHDL entry approach

|----------------------------------------------------------------|
|"Surely didn't every schematic package have various HDL output? |
| |
|Last one I used Intergraph/Veribest/goneaway had Verilog, VHDL &|
|couple of others [. . .] |
|[. . .] |
| |
|[. . .]" | |----------------------------------------------------------------|

Archives are at HTTP://Gloucester.Insomnia247.NL/VHDL/comp.lang.vhdl_on_16th_August_2026_on_archive.USENET.BlueWorldHosting.mbox.txt
and HTTP://Gloucester.Insomnia247.NL/VHDL/comp.arch.fpga_on_17th_August_2026_on_archive.USENET.BlueWorldHosting.mbox.txt
Good luck!
(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)

--- PyGate Linux v1.5.19
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

On Sun, 13 Sep 2026 19:29:29 -0000 (UTC), C?il?n Niocl?s?n Glost?ir <thanks-to@Taf.com> wrote:

I am crossposting as a person who reads a different newsgroup might
give a better answer.

Awe74 wrote in comp.arch.fpga - >|---------------------------------------------------------------------|
|"Hi, |
| |
|I'm looking for an old VeriBest Design Capture release from 1999. |
| |
|I found this old file list, which contains: |
| | >|PWAADP01.ZIP 1,459,067 31/08/99 | >|PWAADP02.ZIP |
|.. | >|PWAADP28.ZIP |
| | >|ANALOG AND DESIGN CAPTURE V99.0A (C) VERIBEST [XX/28] |
| |
|The files appear to be a 28-part split archive of VeriBest Analog and| >|Design Capture V99.0A. |
| |
|I'm particularly interested in finding the original | >|PWAADP01???PWAADP28 ZIP files, or any archive/tape dump containing | >|them. |
| |
|Does anyone here still have these files, or know where this release | >|originally came from (BBS, FTP site, CD, DAT/tape archive, etc.)? |
| |
|I'm also interested in any information about the original file area | >|where these were distributed, possibly under directories such as: |
| |
|/CAD | >|/CAD'S |
|/EDA |
|/PCB |
| |
|The file list I have is dated September 3, 1999, so I'm trying to | >|trace the original source or an archival copy. |
| |
|If you have the files, an old BBS/tape dump, or even just information| >|about where they might have been archived, I'd be very grateful. |
| | >|Thanks!" | >|---------------------------------------------------------------------|

I do not know them. Rick Filipkiewicz gave me the impression that
Mentor bought VeriBest.

He sounds like some arsehole looking for cracked software.

I should have the original instal files backed up somewhere - if he
sends me proof that he has actually bought the software (scan of
invoice, copy of his licence file email) I will look it out.

The Veribest suite cost several thousand pounds in the late 90's, and
the last quote I got from Mentor for the Expedition PCB (with options)
was circa 80K (can't remember if it was USD or GBP). Siemens own it
now, but I doubt if they have reduced the price. It seems to be the
most expensive PCB layout software out there.

--- PyGate Linux v1.5.19
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

If he really wants to buy it then a company which you named could sell
it to him.

(S. HTTP://Gloucester.Insomnia247.NL/ fuer Kontaktdaten!)

--- PyGate Linux v1.5.19
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)

On 9/14/26 18:04, JM wrote:

On Sun, 13 Sep 2026 19:29:29 -0000 (UTC), C¢il¡n Niocl s¡n Glost‚ir <thanks-to@Taf.com> wrote:

I am crossposting as a person who reads a different newsgroup might
give a better answer.

Awe74 wrote in comp.arch.fpga -
|---------------------------------------------------------------------|
|"Hi, |
| |
|I'm looking for an old VeriBest Design Capture release from 1999. |
| |
|I found this old file list, which contains: |
| |
|PWAADP01.ZIP 1,459,067 31/08/99 |
|PWAADP02.ZIP |
|.. |
|PWAADP28.ZIP |
| |
|ANALOG AND DESIGN CAPTURE V99.0A (C) VERIBEST [XX/28] |
| |
|The files appear to be a 28-part split archive of VeriBest Analog and|
|Design Capture V99.0A. |
| |
|I'm particularly interested in finding the original |
|PWAADP01ƒ??PWAADP28 ZIP files, or any archive/tape dump containing |
|them. |
| |
|Does anyone here still have these files, or know where this release |
|originally came from (BBS, FTP site, CD, DAT/tape archive, etc.)? |
| |
|I'm also interested in any information about the original file area |
|where these were distributed, possibly under directories such as: |
| |
|/CAD |
|/CAD'S |
|/EDA |
|/PCB |
| |
|The file list I have is dated September 3, 1999, so I'm trying to |
|trace the original source or an archival copy. |
| |
|If you have the files, an old BBS/tape dump, or even just information|
|about where they might have been archived, I'd be very grateful. |
| |
|Thanks!" |
|---------------------------------------------------------------------|

I do not know them. Rick Filipkiewicz gave me the impression that
Mentor bought VeriBest.

He sounds like some arsehole looking for cracked software.

That's right, everyone a criminal ?. Thankfully, there are now quite
capable open source packages available, so users don;t have to get
locked in to rip off proprietary software.

Same with embedded tools and real time os's, but that gravy train
ended decades ago as well.

I should have the original instal files backed up somewhere - if he
sends me proof that he has actually bought the software (scan of
invoice, copy of his licence file email) I will look it out.

The Veribest suite cost several thousand pounds in the late 90's, and
the last quote I got from Mentor for the Expedition PCB (with options)
was circa 80K (can't remember if it was USD or GBP). Siemens own it
now, but I doubt if they have reduced the price. It seems to be the
most expensive PCB layout software out there.

--- PyGate Linux v1.5.19
* Origin: Dragon's Lair, PyGate NNTP<>Fido Gate (3:633/10)