chrisq <syseng@gfsys.co.uk>wrote:
On 8/30/26 09:24, Jan Panteltje wrote:
john larkin <jl@glen--canyon.com>wrote:
On Sat, 29 Aug 2026 15:09:27 GMT, Jan Panteltje <alien@comet.invalid>wrote:
john larkin <jl@glen--canyon.com>wrote:
On Sat, 29 Aug 2026 11:27:36 GMT, Jan Panteltje <alien@comet.invalid> >>>>> wrote:
john larkin <jl@glen--canyon.com>wrote:
I always forget about dust whan I take a pic. Somehow I don't notice >>>>>>> it in real life first. So I have to brush the dust off and start >>>>>>> again.
https://www.dropbox.com/scl/fi/yfgkmqw2b26sug7ojpm59/SPI_CLK_Dusty.jpg?rlkey=yn6c5qge3m96r1w4rirodfkc6&raw=1
https://www.dropbox.com/scl/fi/3mi7511bg86urvao6i687/SPI_CLK.jpg?rlkey=02242c9asiwn033ceytrjqv10&raw=1
https://www.dropbox.com/scl/fi/ckwar22n2v4u6qsok2yvu/SPI_CLK_2.jpg?rlkey=k1rj1kafuozfo6m5fhzprbylj&raw=1
and it was really hard to keep the probe tip and the ground spring on >>>>>>> the board with one hand and hit a key on the laptop with the other. >>>>>>>
That Rigol fet probe is OK electrically but nasty mechanically.
The signal is from an Efinix T20 FPGA, through a bunch of traces and a >>>>>>> ribbon cable. We tuned the drive strength and speed as best guesses. >>>>>>> Looks pretty good. The next step of drive strength might be a bit >>>>>>> nicer, but this is pretty good.
https://www.dropbox.com/scl/fi/69wwpsoc0o47cidxwust7/B360_20260813_110116.jpg?rlkey=y0sxkzswmgj3wa9lvf9ihbdio&raw=1
What's the big yellow flat thing?
Capacitor? VDR?
PTC self-resetting fuse. The user might, for instance, apply power
backwards and we want the box to survive.
OK I see.
Reverse diode to ground after it?
A TVS. If one of our esteemed customers applies -24 or +60 the TVS
will clamp and maybe fail. A fried/shorted TVS will sacrifice itself
to save the rest of the board, and allow us to assign blame.
HP did that in some of their linear regulator power supplies. A zener
diode of voltage just above the regulated voltage, which would fail,
go short circuit, and blow a fuse. use to think that a bit crude, but
did work. Seen several eamples of that.
On some models, with 115/230 volt line rating, uk line at 245 could
overheat the series regulator transistor, go short, and enable the
zener diode to do it's work.
john larkin <jl@glen--canyon.com>wrote:
On Sat, 29 Aug 2026 15:09:27 GMT, Jan Panteltje <alien@comet.invalid> >>wrote:
john larkin <jl@glen--canyon.com>wrote:
On Sat, 29 Aug 2026 11:27:36 GMT, Jan Panteltje <alien@comet.invalid> >>>>wrote:
john larkin <jl@glen--canyon.com>wrote:
I always forget about dust whan I take a pic. Somehow I don't notice >>>>>>it in real life first. So I have to brush the dust off and start >>>>>>again.
https://www.dropbox.com/scl/fi/yfgkmqw2b26sug7ojpm59/SPI_CLK_Dusty.jpg?rlkey=yn6c5qge3m96r1w4rirodfkc6&raw=1
https://www.dropbox.com/scl/fi/3mi7511bg86urvao6i687/SPI_CLK.jpg?rlkey=02242c9asiwn033ceytrjqv10&raw=1
https://www.dropbox.com/scl/fi/ckwar22n2v4u6qsok2yvu/SPI_CLK_2.jpg?rlkey=k1rj1kafuozfo6m5fhzprbylj&raw=1
and it was really hard to keep the probe tip and the ground spring on >>>>>>the board with one hand and hit a key on the laptop with the other. >>>>>>
That Rigol fet probe is OK electrically but nasty mechanically.
The signal is from an Efinix T20 FPGA, through a bunch of traces and a >>>>>>ribbon cable. We tuned the drive strength and speed as best guesses. >>>>>>Looks pretty good. The next step of drive strength might be a bit >>>>>>nicer, but this is pretty good.
https://www.dropbox.com/scl/fi/69wwpsoc0o47cidxwust7/B360_20260813_110116.jpg?rlkey=y0sxkzswmgj3wa9lvf9ihbdio&raw=1
What's the big yellow flat thing?
Capacitor? VDR?
PTC self-resetting fuse. The user might, for instance, apply power >>>>backwards and we want the box to survive.
OK I see.
Reverse diode to ground after it?
A TVS. If one of our esteemed customers applies -24 or +60 the TVS
will clamp and maybe fail. A fried/shorted TVS will sacrifice itself
to save the rest of the board, and allow us to assign blame.
Too much drop in a series diode?
Power MOSFET as serial protection switch?
A series diode would be OK. I don't trust semiconductors for primary
power protection. I tested a TI e-fuse and it was awful.
We've tried the surface-mount versions before and they are not >>>>reliable.
I had a battle with production about that part. They wanted to kink
the leads, which lifted the ptc up and made it hit the top cover.
I won.
The cool thing about that design is that both boards work perfectly on >>>>rev A, first try, with zero changes. Both have parts on both sides.
One of my guys wants to change one resistor value, to shift some >>>>dissipation and reduce the temperature rise of a linear regulator.
The RP2040 uP and the Efinix FPGA are both awesome parts.
Yes, I may try that in a next project that uses a FPGA.
We embedd the FPGA config into the Pi executable file, so there is a
single USB file drag-and-drop to field upgrade all the code.
At powerup time, we use an SPI block to configure the FPGA and then
use the same SPI to read/write FPGA registers.
I can share our uP/FPGA schematic pages. It wasn't entirely obvious
how to do all that. The Efinix data sheet is like a murder mystery
with clues here and there.
We did a proto board to test that and to test some other circuits and >>parts.
https://www.dropbox.com/scl/fi/npkdfdb4shr2m2jokqa1l/X116_On_Plate.jpg?rlkey=negw6radsojplh0zso6gha2vb&raw=1
Yes you posted that before I remember :-)
I will have to hand solder that.. with wires and adaptors ;-)
john larkin <jl@htigct.com>wrote:
On Sun, 30 Aug 2026 08:24:03 GMT, Jan Panteltje <alien@comet.invalid>wrote:
john larkin <jl@glen--canyon.com>wrote:
On Sat, 29 Aug 2026 15:09:27 GMT, Jan Panteltje <alien@comet.invalid> >>>wrote:
john larkin <jl@glen--canyon.com>wrote:
On Sat, 29 Aug 2026 11:27:36 GMT, Jan Panteltje <alien@comet.invalid> >>>>>wrote:
john larkin <jl@glen--canyon.com>wrote:
I always forget about dust whan I take a pic. Somehow I don't notice >>>>>>>it in real life first. So I have to brush the dust off and start >>>>>>>again.
https://www.dropbox.com/scl/fi/yfgkmqw2b26sug7ojpm59/SPI_CLK_Dusty.jpg?rlkey=yn6c5qge3m96r1w4rirodfkc6&raw=1
https://www.dropbox.com/scl/fi/3mi7511bg86urvao6i687/SPI_CLK.jpg?rlkey=02242c9asiwn033ceytrjqv10&raw=1
https://www.dropbox.com/scl/fi/ckwar22n2v4u6qsok2yvu/SPI_CLK_2.jpg?rlkey=k1rj1kafuozfo6m5fhzprbylj&raw=1
and it was really hard to keep the probe tip and the ground spring on >>>>>>>the board with one hand and hit a key on the laptop with the other. >>>>>>>
That Rigol fet probe is OK electrically but nasty mechanically.
The signal is from an Efinix T20 FPGA, through a bunch of traces and a >>>>>>>ribbon cable. We tuned the drive strength and speed as best guesses. >>>>>>>Looks pretty good. The next step of drive strength might be a bit >>>>>>>nicer, but this is pretty good.
https://www.dropbox.com/scl/fi/69wwpsoc0o47cidxwust7/B360_20260813_110116.jpg?rlkey=y0sxkzswmgj3wa9lvf9ihbdio&raw=1
What's the big yellow flat thing?
Capacitor? VDR?
PTC self-resetting fuse. The user might, for instance, apply power >>>>>backwards and we want the box to survive.
OK I see.
Reverse diode to ground after it?
A TVS. If one of our esteemed customers applies -24 or +60 the TVS
will clamp and maybe fail. A fried/shorted TVS will sacrifice itself
to save the rest of the board, and allow us to assign blame.
Too much drop in a series diode?
Power MOSFET as serial protection switch?
A series diode would be OK. I don't trust semiconductors for primary >>>power protection. I tested a TI e-fuse and it was awful.
We've tried the surface-mount versions before and they are not >>>>>reliable.
I had a battle with production about that part. They wanted to kink >>>>>the leads, which lifted the ptc up and made it hit the top cover.
I won.
The cool thing about that design is that both boards work perfectly on >>>>>rev A, first try, with zero changes. Both have parts on both sides.
One of my guys wants to change one resistor value, to shift some >>>>>dissipation and reduce the temperature rise of a linear regulator.
The RP2040 uP and the Efinix FPGA are both awesome parts.
Yes, I may try that in a next project that uses a FPGA.
We embedd the FPGA config into the Pi executable file, so there is a >>>single USB file drag-and-drop to field upgrade all the code.
At powerup time, we use an SPI block to configure the FPGA and then
use the same SPI to read/write FPGA registers.
I can share our uP/FPGA schematic pages. It wasn't entirely obvious
how to do all that. The Efinix data sheet is like a murder mystery
with clues here and there.
We did a proto board to test that and to test some other circuits and >>>parts.
https://www.dropbox.com/scl/fi/npkdfdb4shr2m2jokqa1l/X116_On_Plate.jpg?rlkey=negw6radsojplh0zso6gha2vb&raw=1
Yes you posted that before I remember :-)
I will have to hand solder that.. with wires and adaptors ;-)
One of my interns introduced us to JLCPCB. Now making PCBs as protos
is cheap and easy.
It's hard to find adapters for a lot of parts. When we do proto PCBs,
we toss in adapters or goofy circuits too.
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