In article <PeMbS.103022$aXr.22087@fx18.ams4>,
Johann 'Myrkraverk' Oskarsson <johann@myrkraverk.invalid> wrote:
...
And why did acc define it signed in the first place? Maybe the CPU only
had signed bytes, or they were faster than unsigned? I wouldn't know as
this is a made up example.
Thank you for your response. I hope to see more responses on this thread.
But, just out of curiosity, why do you way that "this is a made up example" ? To what are you referring and why do you think it was "made up" ?
On 03/08/2026 9:47 AM, Kenny McCormack wrote:
In article <PeMbS.103022$aXr.22087@fx18.ams4>,
Johann 'Myrkraverk' Oskarsson <johann@myrkraverk.invalid> wrote:
...
And why did acc define it signed in the first place? Maybe the CPU only >> had signed bytes, or they were faster than unsigned? I wouldn't know as >> this is a made up example.
Thank you for your response. I hope to see more responses on this thread.
But, just out of curiosity, why do you way that "this is a made up example" ?
To what are you referring and why do you think it was "made up" ?
Because I did not bother to dig up my RISC OS computer, and see what
that C compiler did about the signedness of chars.
It's a high chance that GCC, when ported to ARM for the first time,
was compatible with whatever C compiler the original /Acorn/ team
used, or made.
I believe I have a continuation of that C compiler on my RISC OS
machine. So assuming it still works, I can boot it up, and check
what it does.
Then, we should keep in mind that the /Acorn/ team was used to code
in assembly. I believe most of RISC OS is coded in assembly, and
their original C compiler was -- and had to be -- compatible with
whatever /application binary interface/ they were used to in that
assembly code.
So, that's the reason I believe default ARM char is unsigned. I'm
sure other regulars will be extremely happy to correct me, so let
them. They enjoy that sport.
Also, in that vein, you can easily merge four 8 bit values in
registers into a 32-bit word:
ORR Rd,Rs0,Rs1,LSL#8
ORR Rd, Rd,Rs2,LSL#16
ORR Rd, Rd,Rs3,LSL#24
which sign extension would mess up (you'd have to mask off the sign
bits first).
On 04 Aug 2026 13:13:22 +0100 (BST), Theo wrote:
Also, in that vein, you can easily merge four 8 bit values in
registers into a 32-bit word:
ORR Rd,Rs0,Rs1,LSL#8
ORR Rd, Rd,Rs2,LSL#16
ORR Rd, Rd,Rs3,LSL#24
which sign extension would mess up (you'd have to mask off the sign
bits first).
That?s what happens in general: any kind of bit-twiddling is usually
much easier with unsigned rather than signed integer types (of
whatever size).
I once had to do some inter-process communication between a client?s
online shop system and the payment processor. The code library they
provided was written in Java, so I wrote a wrapper app around that to communicate with the main shop system (which I had written in C++).
(Seasoned Java programmers can probably already guess where this story
is going ...)
About once a week or so, a payment would fail to go through. Took me
quite a few examinations of debug messages before I realized that,
because Java only has signed integers and no unsigned, I was sometimes computing a length field incorrectly due to sign extension.
Put in the necessary masking calls, and all was hunky-dory after that.
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