I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
On Tue, 17 Mar 2026 22:30:01 +0000, someone <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the >engineers I've hung out with could too, John Larkin may be projecting here.
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
What are you designing now?
I designed some PLDs, from PALS to PEELS to the antifuse Actel FPGAs,
but it's mostly grunt work, so I give requirements to kids to type the
VHDL for me. I have an ex-physicist doing that for us now.
What was interesting about the otp Actel parts is that the design was schematic entry, and it had to be right the first time.
Modern FPGA design is like cpu coding: hack it fast and run it and see
what happens and when it doesn't work, fix it.
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's.
Then you only have the one fast carry TPD for the MS18b overflowing
to all 1s when a 1 is clocked into its LSB. One whole clock period
to clock the 1 out of the DFF and meet the setup times for what I
assume is a synchronous LD and its setup for the counters. So that
particular timing criticality is a DFF TPD and a LD setup TSU to
reliably capture the register data. The LD TPD to CLK TSU for the
LS18b counter shouldn't be a problem. This must be very speedy logic
for 150MHz. Do you have a simulator that displays how much margin you
have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the engineers I've hung out with could too, John Larkin may be projecting here.
On 03/20/2026 10:36 PM, Bill Sloman wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's.
Then you only have the one fast carry TPD for the MS18b overflowing
to all 1s when a 1 is clocked into its LSB. One whole clock period
to clock the 1 out of the DFF and meet the setup times for what I
assume is a synchronous LD and its setup for the counters. So that
particular timing criticality is a DFF TPD and a LD setup TSU to
reliably capture the register data. The LD TPD to CLK TSU for the
LS18b counter shouldn't be a problem. This must be very speedy logic
for 150MHz. Do you have a simulator that displays how much margin you
have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
I have a lot of interest in the Bruchla circuit as about things
like transistor nets to effect things like Fourier-style analysis.
The Bruchla circuit among accounts of things like integrators
and differentiators, is for the middling account of dividers,
that otherwise doesn't have exactly a simple ideal circuit.
On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson <ross.a.finlayson@gmail.com> wrote:
On 03/20/2026 10:36 PM, Bill Sloman wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's.
Then you only have the one fast carry TPD for the MS18b overflowing
to all 1s when a 1 is clocked into its LSB. One whole clock period
to clock the 1 out of the DFF and meet the setup times for what I
assume is a synchronous LD and its setup for the counters. So that
particular timing criticality is a DFF TPD and a LD setup TSU to
reliably capture the register data. The LD TPD to CLK TSU for the
LS18b counter shouldn't be a problem. This must be very speedy logic >>>>> for 150MHz. Do you have a simulator that displays how much margin you >>>>> have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
I base the observation on people that I work with, and lately on
hundreds of people that I meet at maker-space meetups.
Many are kids with CE/EE degrees who don't know much about electricity and who don't have jobs.
A Linked-In ad for fpga coders will get hundreds of applicants in a
few days. Circuit designers, not so many. I have a couple of quick
tests to find the rare kid that gets electronics.
I have a lot of interest in the Bruchla circuit as about things
like transistor nets to effect things like Fourier-style analysis.
The Bruchla circuit among accounts of things like integrators
and differentiators, is for the middling account of dividers,
that otherwise doesn't have exactly a simple ideal circuit.
Is there some specific Bruchla frequency divider circuit?
There seem to be a lot of 50-year old Bruchla circuits online. Looks
like mostly audio.
On 22/03/2026 4:29 am, john larkin wrote:
On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson
<ross.a.finlayson@gmail.com> wrote:
On 03/20/2026 10:36 PM, Bill Sloman wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. >>>>>> Then you only have the one fast carry TPD for the MS18b overflowing >>>>>> to all 1s when a 1 is clocked into its LSB. One whole clock period >>>>>> to clock the 1 out of the DFF and meet the setup times for what I
assume is a synchronous LD and its setup for the counters. So that >>>>>> particular timing criticality is a DFF TPD and a LD setup TSU to
reliably capture the register data. The LD TPD to CLK TSU for the
LS18b counter shouldn't be a problem. This must be very speedy logic >>>>>> for 150MHz. Do you have a simulator that displays how much margin you >>>>>> have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>> I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
I base the observation on people that I work with, and lately on
hundreds of people that I meet at maker-space meetups.
You don't like hiring people with a Ph.D. My employers didn't have that >problem.
Many are kids with CE/EE degrees who don't know much about electricity and >> who don't have jobs.
A Linked-In ad for fpga coders will get hundreds of applicants in a
few days. Circuit designers, not so many. I have a couple of quick
tests to find the rare kid that gets electronics.
And presumably also test their willingness to flatter you at every
possible opportunity.
I have a lot of interest in the Bruchla circuit as about things
like transistor nets to effect things like Fourier-style analysis.
The Bruchla circuit among accounts of things like integrators
and differentiators, is for the middling account of dividers,
that otherwise doesn't have exactly a simple ideal circuit.
Is there some specific Bruchla frequency divider circuit?
There seem to be a lot of 50-year old Bruchla circuits online. Looks
like mostly audio.
There are lots of odd ways of implementing frequency dividers.
Synchronous dividers can be made to work at higher frequencies than
ripple carry dividers, and synchronous dividers with fast carry
feed-forward hardware can be designed to count even faster.
Duplicating known hardware solutions inside an FPGA can't be all that >difficult. There are some remarkably fast FPGAs around. When I last
looked they were remarkably expensive, but that was about twenty years ago.
On Mon, 23 Mar 2026 23:49:36 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 4:29 am, john larkin wrote:
On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson
<ross.a.finlayson@gmail.com> wrote:
On 03/20/2026 10:36 PM, Bill Sloman wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. >>>>>>> Then you only have the one fast carry TPD for the MS18b overflowing >>>>>>> to all 1s when a 1 is clocked into its LSB. One whole clock period >>>>>>> to clock the 1 out of the DFF and meet the setup times for what I >>>>>>> assume is a synchronous LD and its setup for the counters. So that >>>>>>> particular timing criticality is a DFF TPD and a LD setup TSU to >>>>>>> reliably capture the register data. The LD TPD to CLK TSU for the >>>>>>> LS18b counter shouldn't be a problem. This must be very speedy logic >>>>>>> for 150MHz. Do you have a simulator that displays how much margin you >>>>>>> have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>> engineers I've hung out with could too, John Larkin may be projecting here.
I base the observation on people that I work with, and lately on
hundreds of people that I meet at maker-space meetups.
You don't like hiring people with a Ph.D. My employers didn't have that
problem.
Many are kids with CE/EE degrees who don't know much about electricity and >>> who don't have jobs.
A Linked-In ad for fpga coders will get hundreds of applicants in a
few days. Circuit designers, not so many. I have a couple of quick
tests to find the rare kid that gets electronics.
And presumably also test their willingness to flatter you at every
possible opportunity.
I have a lot of interest in the Bruchla circuit as about things
like transistor nets to effect things like Fourier-style analysis.
The Bruchla circuit among accounts of things like integrators
and differentiators, is for the middling account of dividers,
that otherwise doesn't have exactly a simple ideal circuit.
Is there some specific Bruchla frequency divider circuit?
There seem to be a lot of 50-year old Bruchla circuits online. Looks
like mostly audio.
There are lots of odd ways of implementing frequency dividers.
Synchronous dividers can be made to work at higher frequencies than
ripple carry dividers, and synchronous dividers with fast carry
feed-forward hardware can be designed to count even faster.
Duplicating known hardware solutions inside an FPGA can't be all that
difficult. There are some remarkably fast FPGAs around. When I last
looked they were remarkably expensive, but that was about twenty years ago.
Mostly people express intent in an HDL, basically say X=X+1, and the
compiler makes that happen. The things inside a modern FPGA look
nothing like 7400-series logic.
I'm doing a DDS frequency synthesizer in a $9 Efinix FPGA, running at
250 MHz. That's neither their fastest nor their cheapest part.
I'm running the DDS, driving a 5-resistor DAC and running a bunch of
other stuff, using 24 mA at 1.2v core supply. It doesn't even feel
warm.
On 24/03/2026 2:20 am, john larkin wrote:
On Mon, 23 Mar 2026 23:49:36 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 4:29 am, john larkin wrote:Mostly people express intent in an HDL, basically say X=X+1, and the
On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson
<ross.a.finlayson@gmail.com> wrote:
On 03/20/2026 10:36 PM, Bill Sloman wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. >>>>>>>> Then you only have the one fast carry TPD for the MS18b overflowing >>>>>>>> to all 1s when a 1 is clocked into its LSB. One whole clock period >>>>>>>> to clock the 1 out of the DFF and meet the setup times for what I >>>>>>>> assume is a synchronous LD and its setup for the counters. So that >>>>>>>> particular timing criticality is a DFF TPD and a LD setup TSU to >>>>>>>> reliably capture the register data. The LD TPD to CLK TSU for the >>>>>>>> LS18b counter shouldn't be a problem. This must be very speedy logic >>>>>>>> for 150MHz. Do you have a simulator that displays how much margin you >>>>>>>> have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
I base the observation on people that I work with, and lately on
hundreds of people that I meet at maker-space meetups.
You don't like hiring people with a Ph.D. My employers didn't have that
problem.
Many are kids with CE/EE degrees who don't know much about electricity and >>>> who don't have jobs.
A Linked-In ad for fpga coders will get hundreds of applicants in a
few days. Circuit designers, not so many. I have a couple of quick
tests to find the rare kid that gets electronics.
And presumably also test their willingness to flatter you at every
possible opportunity.
I have a lot of interest in the Bruchla circuit as about things
like transistor nets to effect things like Fourier-style analysis.
The Bruchla circuit among accounts of things like integrators
and differentiators, is for the middling account of dividers,
that otherwise doesn't have exactly a simple ideal circuit.
Is there some specific Bruchla frequency divider circuit?
There seem to be a lot of 50-year old Bruchla circuits online. Looks
like mostly audio.
There are lots of odd ways of implementing frequency dividers.
Synchronous dividers can be made to work at higher frequencies than
ripple carry dividers, and synchronous dividers with fast carry
feed-forward hardware can be designed to count even faster.
Duplicating known hardware solutions inside an FPGA can't be all that
difficult. There are some remarkably fast FPGAs around. When I last
looked they were remarkably expensive, but that was about twenty years ago. >>
compiler makes that happen. The things inside a modern FPGA look
nothing like 7400-series logic.
Why would they? I tended to used 100k ECL and ECLinPS when it became >available. It was a whole lot faster that 7400-series logic, and a lot >better at driving terminated transmission lines.
Because I worked on electron-beam microfabricators and electron-bream >testers for some of my time at Cambridge I did have some idea of what
the working surface of integrated circuit looked like, but not enough to
be able to distinguish a TLL part from an ECL part or any of the
flavours of field programmable devices.
I'm doing a DDS frequency synthesizer in a $9 Efinix FPGA, running at
250 MHz. That's neither their fastest nor their cheapest part.
We could have done that in ECLinPs in 1995. It wouldn't have been all
that expensive.
On Tue, 24 Mar 2026 23:04:04 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 24/03/2026 2:20 am, john larkin wrote:
On Mon, 23 Mar 2026 23:49:36 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 4:29 am, john larkin wrote:
On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson
<ross.a.finlayson@gmail.com> wrote:
On 03/20/2026 10:36 PM, Bill Sloman wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. >>>>>>>>> Then you only have the one fast carry TPD for the MS18b overflowing >>>>>>>>> to all 1s when a 1 is clocked into its LSB. One whole clock period >>>>>>>>> to clock the 1 out of the DFF and meet the setup times for what I >>>>>>>>> assume is a synchronous LD and its setup for the counters. So that >>>>>>>>> particular timing criticality is a DFF TPD and a LD setup TSU to >>>>>>>>> reliably capture the register data. The LD TPD to CLK TSU for the >>>>>>>>> LS18b counter shouldn't be a problem. This must be very speedy logic >>>>>>>>> for 150MHz. Do you have a simulator that displays how much margin you >>>>>>>>> have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
I base the observation on people that I work with, and lately on
hundreds of people that I meet at maker-space meetups.
You don't like hiring people with a Ph.D. My employers didn't have that >>>> problem.
Many are kids with CE/EE degrees who don't know much about electricity and
who don't have jobs.
A Linked-In ad for fpga coders will get hundreds of applicants in a
few days. Circuit designers, not so many. I have a couple of quick
tests to find the rare kid that gets electronics.
And presumably also test their willingness to flatter you at every
possible opportunity.
I have a lot of interest in the Bruchla circuit as about things
like transistor nets to effect things like Fourier-style analysis. >>>>>>
The Bruchla circuit among accounts of things like integrators
and differentiators, is for the middling account of dividers,
that otherwise doesn't have exactly a simple ideal circuit.
Is there some specific Bruchla frequency divider circuit?
There seem to be a lot of 50-year old Bruchla circuits online. Looks >>>>> like mostly audio.
There are lots of odd ways of implementing frequency dividers.
Synchronous dividers can be made to work at higher frequencies than
ripple carry dividers, and synchronous dividers with fast carry
feed-forward hardware can be designed to count even faster.
Duplicating known hardware solutions inside an FPGA can't be all that
difficult. There are some remarkably fast FPGAs around. When I last
looked they were remarkably expensive, but that was about twenty years ago.
Mostly people express intent in an HDL, basically say X=X+1, and the
compiler makes that happen. The things inside a modern FPGA look
nothing like 7400-series logic.
Why would they? I tended to used 100k ECL and ECLinPS when it became
available. It was a whole lot faster that 7400-series logic, and a lot
better at driving terminated transmission lines.
Because I worked on electron-beam microfabricators and electron-bream
testers for some of my time at Cambridge I did have some idea of what
the working surface of integrated circuit looked like, but not enough to
be able to distinguish a TLL part from an ECL part or any of the
flavours of field programmable devices.
I'm doing a DDS frequency synthesizer in a $9 Efinix FPGA, running at
250 MHz. That's neither their fastest nor their cheapest part.
We could have done that in ECLinPs in 1995. It wouldn't have been all
that expensive.
Imagine making a 32-bit ECL register driving a 32-bit phase
accumulator driving a 10K-word sine lookup table driving an
ECL-compatible DAC. With maybe 1000 pulldown resistors.
With its own Honda generator and a bunch of fans.
Gosh, you *do* have a sense of humor.
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote:Gosh Bill, you are wonderful. You are great at everything.
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here. >>
I'm certainly not great at writing VHDL. There's a VHDL text-book on my >bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
I designed some PLDs, from PALS to PEELS to the antifuse Actel FPGAs,
but it's mostly grunt work, so I give requirements to kids to type the
VHDL for me. I have an ex-physicist doing that for us now.
Getting anything to work is mostly grunt work.
What was interesting about the otp Actel parts is that the design was
schematic entry, and it had to be right the first time.
One time programmable parts are like that. It's nice to be able simulate
the design before you blow the fuses.
Modern FPGA design is like cpu coding: hack it fast and run it and see
what happens and when it doesn't work, fix it.
Reprogrammable parts are lot more forgiving. Hacking it fast isn't a
great way to design stuff. It too easy to dive down the wrong rabbit
hole, and keep digging, when you ought sit back and think it out again.
Big software projects have exactly the same problem. Windows is a
steaming heap of legacy software.
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>> I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I designed some PLDs, from PALS to PEELS to the antifuse Actel FPGAs,
but it's mostly grunt work, so I give requirements to kids to type the
VHDL for me. I have an ex-physicist doing that for us now.
Getting anything to work is mostly grunt work.
What was interesting about the otp Actel parts is that the design was
schematic entry, and it had to be right the first time.
One time programmable parts are like that. It's nice to be able simulate
the design before you blow the fuses.
We invented our triggered, phaselocked LC oscillator, which is pretty
gnarly. We progammed the loop into an Actel and it locked first try.
The OTPs are like laying out a PCB: check it hard and get it right. At
least you can hack a PCB.
Modern FPGA design is like cpu coding: hack it fast and run it and see
what happens and when it doesn't work, fix it.
Reprogrammable parts are lot more forgiving. Hacking it fast isn't a
great way to design stuff. It too easy to dive down the wrong rabbit
hole, and keep digging, when you ought sit back and think it out again.
Big software projects have exactly the same problem. Windows is a
steaming heap of legacy software.
Garbage, but continually being repaired.
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>> engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my
bookshelf - bought for a project which didn't come off - but the stuff I >>> did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my >>>> bookshelf - bought for a project which didn't come off - but the stuff I >>>> did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm >>>> not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my >>>>> bookshelf - bought for a project which didn't come off - but the stuff I >>>>> did type was in a much less powerful language, but powerful enough to >>>>> get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm >>>>> not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into
advanced electronic design it doesn't look promising.
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>>>
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my >>>>>> bookshelf - bought for a project which didn't come off - but the stuff I >>>>>> did type was in a much less powerful language, but powerful enough to >>>>>> get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm >>>>>> not an attractive employee.
Join one of those maker space things, meet some people, offer to help >>>>> for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know >>>> of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into
advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of
people who want to build things that use electronics, and those people
aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They
go to meetups to pitch their ideas and maybe meet people who could
help.
Studio 45 near here has an occasional meetup with 500 people, free
food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant
and recommended Phil's book. And listened to yet another pitch for AI circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things.
The point is that you could show up, and meet people who need
electronics, and see what happens.
Or don't.
[1] It's impressive how few people are good at electronic design.
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the >>>>>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my >>>>>>> bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to >>>>>>> get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm >>>>>>> not an attractive employee.
Join one of those maker space things, meet some people, offer to help >>>>>> for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know >>>>> of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am >>> a tolerably competent carpenter so I might fit in. As a route into
advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of
people who want to build things that use electronics, and those people
aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They
go to meetups to pitch their ideas and maybe meet people who could
help.
Studio 45 near here has an occasional meetup with 500 people, free
food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant
and recommended Phil's book. And listened to yet another pitch for AI
circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things.
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed >electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
[1] It's impressive how few people are good at electronic design.
Even more impressive that you seem to think you can make that statement.
If you don't think that a classical emitter-coupled monostable can work, >your status as a judge of electronic design quality can't be all that high.
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>>>>> *slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing.
FPGAs are great, but there's a cultural gap between people who draw >>>>>>>>>>> and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to >>>>>>>> get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help >>>>>>> for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know >>>>>> of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am >>>> a tolerably competent carpenter so I might fit in. As a route into
advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of
people who want to build things that use electronics, and those people
aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They
go to meetups to pitch their ideas and maybe meet people who could
help.
Studio 45 near here has an occasional meetup with 500 people, free
food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant
and recommended Phil's book. And listened to yet another pitch for AI
circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things.
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed
electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
[1] It's impressive how few people are good at electronic design.
Even more impressive that you seem to think you can make that statement.
If you don't think that a classical emitter-coupled monostable can work,
your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often
useful in this modern world. I didn't like your version because the
input trigger had to be delicately tuned to fire it, and it really
amplified the input pulse more than it one-shotted. It was Spice tuned
until it appeared to work.
There are far better, easier, cheaper, more deliberate ways to make a
fast one-shot these days.
I like to clock a 1 ns Tiny Logic flop and then have it reset itself.
Or use a '123 chip if there's no hurry. They are all pokey.
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing. >>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything.
I'm certainly not great at writing VHDL. There's a VHDL text-book on my
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to >>>>>>>>> get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help >>>>>>>> for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know >>>>>>> of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am >>>>> a tolerably competent carpenter so I might fit in. As a route into
advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of
people who want to build things that use electronics, and those people >>>> aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They
go to meetups to pitch their ideas and maybe meet people who could
help.
Studio 45 near here has an occasional meetup with 500 people, free
food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant
and recommended Phil's book. And listened to yet another pitch for AI
circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things.
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed
electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a
brilliant circuit designer, you feel insulted, though you should be used
to that by now.
That circuit can certainly work; it's classic=ancient. But not often[1] It's impressive how few people are good at electronic design.
Even more impressive that you seem to think you can make that statement. >>> If you don't think that a classical emitter-coupled monostable can work, >>> your status as a judge of electronic design quality can't be all that high. >>
useful in this modern world. I didn't like your version because the
input trigger had to be delicately tuned to fire it, and it really
amplified the input pulse more than it one-shotted. It was Spice tuned
until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't
spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the >normally-on transistor and push enough current into the timing capacitor
to get the one-shot action, and the amplification is incidental to that.
You didn't recognise the circuit, couldn't see how it worked, and have
been trying to deny this obvious point ever since.
This isn't the kind
of comment you like reading, and will claim that you are being insulted. >Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a
fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand
I like to clock a 1 ns Tiny Logic flop and then have it reset itself.
I'm sure you would.
Or use a '123 chip if there's no hurry. They are all pokey.
The '121 chip is a better monostable, with a much more predictable and >stable on time, though it is not retriggerable.
Current steering logic doesn't mess up the power rails anything like as >much.
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>I'm certainly not great at writing VHDL. There's a VHDL text-book on my
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing. >>>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help >>>>>>>>> for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know >>>>>>>> of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am >>>>>> a tolerably competent carpenter so I might fit in. As a route into >>>>>> advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of
people who want to build things that use electronics, and those people >>>>> aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They >>>>> go to meetups to pitch their ideas and maybe meet people who could
help.
Studio 45 near here has an occasional meetup with 500 people, free
food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant >>>>> and recommended Phil's book. And listened to yet another pitch for AI >>>>> circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things.
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed
electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a
brilliant circuit designer, you feel insulted, though you should be used
to that by now.
[1] It's impressive how few people are good at electronic design.
Even more impressive that you seem to think you can make that statement. >>>> If you don't think that a classical emitter-coupled monostable can work, >>>> your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often
useful in this modern world. I didn't like your version because the
input trigger had to be delicately tuned to fire it, and it really
amplified the input pulse more than it one-shotted. It was Spice tuned
until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't
spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the
normally-on transistor and push enough current into the timing capacitor
to get the one-shot action, and the amplification is incidental to that.
You didn't recognise the circuit, couldn't see how it worked, and have
been trying to deny this obvious point ever since.
That circuit is in the 1964 GE Transistor Manual (7th edition, $2). Transistors used to be expensive so their use was minimized. Nowadays
they cost about nothing.
This isn't the kind
of comment you like reading, and will claim that you are being insulted.
Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a
fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand
I usually design circuits that I understand, but what matters is that
they work.
With Spice or experiment, one can profitably design a circuit that you
don't understand. I have a cool new sensor simulator circuit that I
don't understand.
I like to clock a 1 ns Tiny Logic flop and then have it reset itself.
I'm sure you would.
Or use a '123 chip if there's no hurry. They are all pokey.
The '121 chip is a better monostable, with a much more predictable and
stable on time, though it is not retriggerable.
The SN74LVC1G123 seems to be the fastest official one-shot around. At
3.3 volts, Tpd is 12 ns max and the min output pulse width is about
100 ns. OK for blinking LEDs and such. The self-clearing Tiny flop can
get down around 1ns+2ns.
Current steering logic doesn't mess up the power rails anything like as
much.
Just costs 30x as much.
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>I'm certainly not great at writing VHDL. There's a VHDL text-book on my
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>>
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing. >>>>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>>
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into >>>>>>> advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of
people who want to build things that use electronics, and those people >>>>>> aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They >>>>>> go to meetups to pitch their ideas and maybe meet people who could >>>>>> help.
Studio 45 near here has an occasional meetup with 500 people, free >>>>>> food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant >>>>>> and recommended Phil's book. And listened to yet another pitch for AI >>>>>> circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things.
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed >>>>> electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a
brilliant circuit designer, you feel insulted, though you should be used >>> to that by now.
[1] It's impressive how few people are good at electronic design.
Even more impressive that you seem to think you can make that statement. >>>>> If you don't think that a classical emitter-coupled monostable can work, >>>>> your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often
useful in this modern world. I didn't like your version because the
input trigger had to be delicately tuned to fire it, and it really
amplified the input pulse more than it one-shotted. It was Spice tuned >>>> until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't
spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the
normally-on transistor and push enough current into the timing capacitor >>> to get the one-shot action, and the amplification is incidental to that. >>>
You didn't recognise the circuit, couldn't see how it worked, and have
been trying to deny this obvious point ever since.
That circuit is in the 1964 GE Transistor Manual (7th edition, $2).
Transistors used to be expensive so their use was minimized. Nowadays
they cost about nothing.
Using a broad-band transistor in a classic circuit can give you a much >shorter pulse. Broad-band transistors aren't all that cheap, and there >aren't as many of them around as there used to be, but it can be a
useful option.
This isn't the kind
of comment you like reading, and will claim that you are being insulted. >>> Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a
fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand
I usually design circuits that I understand, but what matters is that
they work.
With Spice or experiment, one can profitably design a circuit that you
don't understand. I have a cool new sensor simulator circuit that I
don't understand.
You really don't want to. They have a nasty habit of doing something >unexpected at inconvenient moments.
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>I'm certainly not great at writing VHDL. There's a VHDL text-book on my
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>>>
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing. >>>>>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>>>
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into >>>>>>>> advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of >>>>>>> people who want to build things that use electronics, and those people >>>>>>> aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They >>>>>>> go to meetups to pitch their ideas and maybe meet people who could >>>>>>> help.
Studio 45 near here has an occasional meetup with 500 people, free >>>>>>> food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant >>>>>>> and recommended Phil's book. And listened to yet another pitch for AI >>>>>>> circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things. >>>>>>>
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed >>>>>> electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a
brilliant circuit designer, you feel insulted, though you should be used >>>> to that by now.
[1] It's impressive how few people are good at electronic design. >>>>>>Even more impressive that you seem to think you can make that statement. >>>>>> If you don't think that a classical emitter-coupled monostable can work, >>>>>> your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often >>>>> useful in this modern world. I didn't like your version because the
input trigger had to be delicately tuned to fire it, and it really
amplified the input pulse more than it one-shotted. It was Spice tuned >>>>> until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't >>>> spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the >>>> normally-on transistor and push enough current into the timing capacitor >>>> to get the one-shot action, and the amplification is incidental to that. >>>>
You didn't recognise the circuit, couldn't see how it worked, and have >>>> been trying to deny this obvious point ever since.
That circuit is in the 1964 GE Transistor Manual (7th edition, $2).
Transistors used to be expensive so their use was minimized. Nowadays
they cost about nothing.
Using a broad-band transistor in a classic circuit can give you a much
shorter pulse. Broad-band transistors aren't all that cheap, and there
aren't as many of them around as there used to be, but it can be a
useful option.
This isn't the kind
of comment you like reading, and will claim that you are being insulted. >>>> Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a >>>>> fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand
I usually design circuits that I understand, but what matters is that
they work.
With Spice or experiment, one can profitably design a circuit that you
don't understand. I have a cool new sensor simulator circuit that I
don't understand.
You really don't want to. They have a nasty habit of doing something
unexpected at inconvenient moments.
That's not a nasty habit, it's a talent that I practice and teach.
Given an enormous space of undiscovered ideas, one profits from a
method of exploring them in parallel with minimal filtering.
But inconvenient to who? Certainly not to me. Inventing things is fun
and profitable.
It is an interesting question: does one understand then invent, or
invent and then understand? Great scientific and practical ideas seem
to be mostly invent or discover first, understand after.
The Plutonium book is full of examples.
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>I'm certainly not great at writing VHDL. There's a VHDL text-book on my
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>>>>
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains.
After the boys code this, the tools can verify timing. >>>>>>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>>>>
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into >>>>>>>>> advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of >>>>>>>> people who want to build things that use electronics, and those people >>>>>>>> aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They >>>>>>>> go to meetups to pitch their ideas and maybe meet people who could >>>>>>>> help.
Studio 45 near here has an occasional meetup with 500 people, free >>>>>>>> food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant >>>>>>>> and recommended Phil's book. And listened to yet another pitch for AI >>>>>>>> circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things. >>>>>>>>
The point is that you could show up, and meet people who need
electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed >>>>>>> electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a
brilliant circuit designer, you feel insulted, though you should be used >>>>> to that by now.
[1] It's impressive how few people are good at electronic design. >>>>>>>Even more impressive that you seem to think you can make that statement.
If you don't think that a classical emitter-coupled monostable can work,
your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often >>>>>> useful in this modern world. I didn't like your version because the >>>>>> input trigger had to be delicately tuned to fire it, and it really >>>>>> amplified the input pulse more than it one-shotted. It was Spice tuned >>>>>> until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't >>>>> spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the >>>>> normally-on transistor and push enough current into the timing capacitor >>>>> to get the one-shot action, and the amplification is incidental to that. >>>>>
You didn't recognise the circuit, couldn't see how it worked, and have >>>>> been trying to deny this obvious point ever since.
That circuit is in the 1964 GE Transistor Manual (7th edition, $2).
Transistors used to be expensive so their use was minimized. Nowadays
they cost about nothing.
Using a broad-band transistor in a classic circuit can give you a much
shorter pulse. Broad-band transistors aren't all that cheap, and there
aren't as many of them around as there used to be, but it can be a
useful option.
This isn't the kind
of comment you like reading, and will claim that you are being insulted. >>>>> Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a >>>>>> fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand
I usually design circuits that I understand, but what matters is that
they work.
With Spice or experiment, one can profitably design a circuit that you >>>> don't understand. I have a cool new sensor simulator circuit that I
don't understand.
You really don't want to. They have a nasty habit of doing something
unexpected at inconvenient moments.
That's not a nasty habit, it's a talent that I practice and teach.
That's a really nasty habit. Encouraging people to build circuits that
can go wrong when they run into a situation that the designer hadn't >expected is - to put it kindly - unwise.
Given an enormous space of undiscovered ideas, one profits from a
method of exploring them in parallel with minimal filtering.
But one you have "discovered" your original idea, you do need to explore >it's ramifications in detail, and thoroughly understand how it works.
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>I'm certainly not great at writing VHDL. There's a VHDL text-book on my
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone
<cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>>>>>
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain.
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains. >>>>>>>>>>>>>>>>>
After the boys code this, the tools can verify timing. >>>>>>>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>>>>>
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into >>>>>>>>>> advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of >>>>>>>>> people who want to build things that use electronics, and those people
aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They >>>>>>>>> go to meetups to pitch their ideas and maybe meet people who could >>>>>>>>> help.
Studio 45 near here has an occasional meetup with 500 people, free >>>>>>>>> food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant >>>>>>>>> and recommended Phil's book. And listened to yet another pitch for AI >>>>>>>>> circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things. >>>>>>>>>
The point is that you could show up, and meet people who need >>>>>>>>> electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed >>>>>>>> electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a
brilliant circuit designer, you feel insulted, though you should be used >>>>>> to that by now.
[1] It's impressive how few people are good at electronic design. >>>>>>>>Even more impressive that you seem to think you can make that statement.
If you don't think that a classical emitter-coupled monostable can work,
your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often >>>>>>> useful in this modern world. I didn't like your version because the >>>>>>> input trigger had to be delicately tuned to fire it, and it really >>>>>>> amplified the input pulse more than it one-shotted. It was Spice tuned >>>>>>> until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't >>>>>> spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the >>>>>> normally-on transistor and push enough current into the timing capacitor >>>>>> to get the one-shot action, and the amplification is incidental to that. >>>>>>
You didn't recognise the circuit, couldn't see how it worked, and have >>>>>> been trying to deny this obvious point ever since.
That circuit is in the 1964 GE Transistor Manual (7th edition, $2).
Transistors used to be expensive so their use was minimized. Nowadays >>>>> they cost about nothing.
Using a broad-band transistor in a classic circuit can give you a much >>>> shorter pulse. Broad-band transistors aren't all that cheap, and there >>>> aren't as many of them around as there used to be, but it can be a
useful option.
This isn't the kindI usually design circuits that I understand, but what matters is that >>>>> they work.
of comment you like reading, and will claim that you are being insulted. >>>>>> Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a >>>>>>> fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand >>>>>
With Spice or experiment, one can profitably design a circuit that you >>>>> don't understand. I have a cool new sensor simulator circuit that I
don't understand.
You really don't want to. They have a nasty habit of doing something
unexpected at inconvenient moments.
That's not a nasty habit, it's a talent that I practice and teach.
That's a really nasty habit. Encouraging people to build circuits that
can go wrong when they run into a situation that the designer hadn't
expected is - to put it kindly - unwise.
Invention is precisely running into - running toward - the unexpected.
Sometimes that's accidental, but can be deliberately provoked.
Inventing needs the right skills and personality but improves with
practice in the right environment. Books have been written about that.
Some people invent things. Some intelligent and (over)educated people actively resent invention, because they can't do it.
Given an enormous space of undiscovered ideas, one profits from a
method of exploring them in parallel with minimal filtering.
But one you have "discovered" your original idea, you do need to explore
it's ramifications in detail, and thoroughly understand how it works.
Understanding how it works is helpful but not mandatory.
It is prudent to do the grunt work to make it economic and reliable; theory and
understanding and simulation can help with those.
In the big picture, we never really understand how anything works.
On 1/04/2026 7:06 pm, john larkin wrote:
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>I'm certainly not great at writing VHDL. There's a VHDL text-book on my
wrote:
On 20/03/2026 4:05 am, john larkin wrote:
On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>>>>>>
I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
Yes, loadable up-counter with carry chain. >>>>>>>>>>>>>>>>>>
This would be in an FPGA, so the diagram is just a concept. The
reality will be VHDL code. And the FPGA boys use the Wishbone
architecture and want the counter to be 32 bits, which is OK with me.
We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
I expect we could do a divider in that ballpark. The T20 is in the
*slow* Efinix family.
I think the T20 has 18-bit fast carry chains. >>>>>>>>>>>>>>>>>>
After the boys code this, the tools can verify timing. >>>>>>>>>>>>>>>>>>
FPGAs are great, but there's a cultural gap between people who draw
and people who type.
Can't say I've noticed that, but since I can do both, and most of the
engineers I've hung out with could too, John Larkin may be projecting here.
Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>>>>>>
bookshelf - bought for a project which didn't come off - but the stuff I
did type was in a much less powerful language, but powerful enough to
get the chip to do what I wanted it to.
What are you designing now?
Absolutely nothing. I do fish for work from time to time, but at 83 I'm
not an attractive employee.
Join one of those maker space things, meet some people, offer to help
for free, see what happens.
I'm active on the committee of NSW branch of the IEEE but I don't know
of any maker space things in Sydney.
Hey, you could google
maker spaces sydney australia
https://makerspaces.com.au/nsw/sydney
So they exist. Leather work and needle work (sewing) are supported. I am
a tolerably competent carpenter so I might fit in. As a route into >>>>>>>>>>> advanced electronic design it doesn't look promising.
We have some of that handicraft stuff here, but we have a lot of >>>>>>>>>> people who want to build things that use electronics, and those people
aren't usually very good circuit designers. [1]
Some of them are actual startups with an idea and some funding. They >>>>>>>>>> go to meetups to pitch their ideas and maybe meet people who could >>>>>>>>>> help.
Studio 45 near here has an occasional meetup with 500 people, free >>>>>>>>>> food and beer. We might sponsor one.
We had a cool one at a Rivian facility. I met a photonics consultant >>>>>>>>>> and recommended Phil's book. And listened to yet another pitch for AI
circuit/pcb design.
There's one coming up in a pier on the SF Bay, an ocean
instrumentetion outfit. That should be fun.
I do one or two meetups per month and meet lots of Young Things. >>>>>>>>>>
The point is that you could show up, and meet people who need >>>>>>>>>> electronics, and see what happens.
If I showed up at the right meetings, I might meet people who needed >>>>>>>>> electronics. The odds don't look great.
Or don't.
That would seem to be the rational choice.
Exactly. Do nothing. Just post insults on forums all day.
I post information. When it doesn't inform people that you are a >>>>>>> brilliant circuit designer, you feel insulted, though you should be used
to that by now.
[1] It's impressive how few people are good at electronic design. >>>>>>>>>Even more impressive that you seem to think you can make that statement.
If you don't think that a classical emitter-coupled monostable can work,
your status as a judge of electronic design quality can't be all that high.
That circuit can certainly work; it's classic=ancient. But not often >>>>>>>> useful in this modern world. I didn't like your version because the >>>>>>>> input trigger had to be delicately tuned to fire it, and it really >>>>>>>> amplified the input pulse more than it one-shotted. It was Spice tuned >>>>>>>> until it appeared to work.
Many applications have well-defined trigger pulses. I certainly didn't >>>>>>> spend any time "deliberately tuning" the circuit.
The trigger pulse has to be big enough and fast enough to turn off the >>>>>>> normally-on transistor and push enough current into the timing capacitor
to get the one-shot action, and the amplification is incidental to that.
You didn't recognise the circuit, couldn't see how it worked, and have >>>>>>> been trying to deny this obvious point ever since.
That circuit is in the 1964 GE Transistor Manual (7th edition, $2). >>>>>> Transistors used to be expensive so their use was minimized. Nowadays >>>>>> they cost about nothing.
Using a broad-band transistor in a classic circuit can give you a much >>>>> shorter pulse. Broad-band transistors aren't all that cheap, and there >>>>> aren't as many of them around as there used to be, but it can be a
useful option.
This isn't the kindI usually design circuits that I understand, but what matters is that >>>>>> they work.
of comment you like reading, and will claim that you are being insulted.
Tough. This isn't some kind of mutual approbation society
There are far better, easier, cheaper, more deliberate ways to make a >>>>>>>> fast one-shot these days.
Which is to say, to make a one-shot whose action you can understand >>>>>>
With Spice or experiment, one can profitably design a circuit that you >>>>>> don't understand. I have a cool new sensor simulator circuit that I >>>>>> don't understand.
You really don't want to. They have a nasty habit of doing something >>>>> unexpected at inconvenient moments.
That's not a nasty habit, it's a talent that I practice and teach.
That's a really nasty habit. Encouraging people to build circuits that
can go wrong when they run into a situation that the designer hadn't
expected is - to put it kindly - unwise.
Invention is precisely running into - running toward - the unexpected.
That's a bizarre way of looking at it. It's doing something in a way
that hasn't been done before, but it is goal directed, and you wouldn't >start the process if you didn't have a pretty clear idea of what you
wanted to do, if not exactly how you were going to do it.
Sometimes that's accidental, but can be deliberately provoked.
Inventing needs the right skills and personality but improves with
practice in the right environment. Books have been written about that.
None of them useful enough to have been touted at places that encouraged >inventions and applying for patents. EMI Central Research was just such
a place, and I worked there for three years without ever running into
such a book. The histories of Bell Labs
https://en.wikipedia.org/wiki/The_Idea_Factory
didn't mention any such book either. People will write books with the >flimsiest of justifications if they think the product will sell.
Teaching people how to make genuine inventions would be a very good
thing if you could do it, and a lot of confidence tricksters claim that
they can. The evidence supporting such claims doesn't seem to exist.
Some people invent things. Some intelligent and (over)educated people
actively resent invention, because they can't do it.
I can't say that I've met any of them. My father and two of my friends
have each got their names onto about 25 patents and none of them ever
talked about people resenting that work.
Given an enormous space of undiscovered ideas, one profits from a
method of exploring them in parallel with minimal filtering.
At EMI Central Research we were encourage to submit patent queries. One
of my colleagues put in a record number of patent queries - about fifty
in one year - and was seen as having rather poor judgement. None of them >turned into a patent. He would have benefited from better filtering.
On Thu, 2 Apr 2026 02:13:38 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 7:06 pm, john larkin wrote:
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
Invention is precisely running into - running toward - the unexpected.
That's a bizarre way of looking at it. It's doing something in a way
that hasn't been done before, but it is goal directed, and you wouldn't
start the process if you didn't have a pretty clear idea of what you
wanted to do, if not exactly how you were going to do it.
I strongly disagree; that is backwards. Sometimes we imagine products
or circuits that nobody ever wanted or expected. It just happens
sometimes at 2AM.
I have a folder full of ideas, most speculative and unexpected and
probably dumb.
We hire smart kids, college students, to explore them
and write up a report on the possible uses, competitors specs and
pricing, any interesting offshoots that occur to them. They get a
fixed fee when they turn in the report.
Sometimes that's accidental, but can be deliberately provoked.
Inventing needs the right skills and personality but improves with
practice in the right environment. Books have been written about that.
None of them useful enough to have been touted at places that encouraged
inventions and applying for patents. EMI Central Research was just such
a place, and I worked there for three years without ever running into
such a book. The histories of Bell Labs
https://en.wikipedia.org/wiki/The_Idea_Factory
I have that one; good book.
Someone said that all the great inventions at Bell in those days were
done by people who ate lunch with Harry Nyquist.
didn't mention any such book either. People will write books with the
flimsiest of justifications if they think the product will sell.
Teaching people how to make genuine inventions would be a very good
thing if you could do it, and a lot of confidence tricksters claim that
they can. The evidence supporting such claims doesn't seem to exist.
The real evidence is purchase orders.
Some people invent things. Some intelligent and (over)educated people
actively resent invention, because they can't do it.
I can't say that I've met any of them. My father and two of my friends
have each got their names onto about 25 patents and none of them ever
talked about people resenting that work.
Given an enormous space of undiscovered ideas, one profits from a
method of exploring them in parallel with minimal filtering.
At EMI Central Research we were encourage to submit patent queries. One
of my colleagues put in a record number of patent queries - about fifty
in one year - and was seen as having rather poor judgement. None of them
turned into a patent. He would have benefited from better filtering.
The real evidence is purchase orders.
On 2/04/2026 3:12 am, john larkin wrote:
On Thu, 2 Apr 2026 02:13:38 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 7:06 pm, john larkin wrote:
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote:
On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
<snip>
Invention is precisely running into - running toward - the unexpected.
That's a bizarre way of looking at it. It's doing something in a way
that hasn't been done before, but it is goal directed, and you wouldn't
start the process if you didn't have a pretty clear idea of what you
wanted to do, if not exactly how you were going to do it.
I strongly disagree; that is backwards. Sometimes we imagine products
or circuits that nobody ever wanted or expected. It just happens
sometimes at 2AM.
And very few of them look sensible after the sun has come up.
I have a folder full of ideas, most speculative and unexpected and
probably dumb.
If you knew a bit more, it would be a much thinner folder.
We hire smart kids, college students, to explore them
and write up a report on the possible uses, competitors specs and
pricing, any interesting offshoots that occur to them. They get a
fixed fee when they turn in the report.
An expensive self-indulgence.
Sometimes that's accidental, but can be deliberately provoked.
Inventing needs the right skills and personality but improves with
practice in the right environment. Books have been written about that.
None of them useful enough to have been touted at places that encouraged >>> inventions and applying for patents. EMI Central Research was just such
a place, and I worked there for three years without ever running into
such a book. The histories of Bell Labs
https://en.wikipedia.org/wiki/The_Idea_Factory
I have that one; good book.
Someone said that all the great inventions at Bell in those days were
done by people who ate lunch with Harry Nyquist.
didn't mention any such book either. People will write books with the
flimsiest of justifications if they think the product will sell.
Teaching people how to make genuine inventions would be a very good
thing if you could do it, and a lot of confidence tricksters claim that
they can. The evidence supporting such claims doesn't seem to exist.
The real evidence is purchase orders.
People don't give you purchase orders for patents. They buy products.
A good and patentable idea can be central to a product, but inept >development can wreck the best of ideas. The Lintech electron beam
tester was based on a patented idea of their boss, whose name was on the >patent (which he'd got to own). He cheap-skated on the development to
such an extent that one of his ex-engineers was able to build a pretty
much identical machine which destroyed his business - nobody ordered a >Lintech machine after the Schlumberger competitor hit the market, and
after Lintech had delivered the last of the machine it had sold they
went bankrupt. Mike Engelhart - of LTSpice fame - worked on that project.
Some people invent things. Some intelligent and (over)educated people
actively resent invention, because they can't do it.
I can't say that I've met any of them. My father and two of my friends
have each got their names onto about 25 patents and none of them ever
talked about people resenting that work.
Given an enormous space of undiscovered ideas, one profits from a
method of exploring them in parallel with minimal filtering.
At EMI Central Research we were encourage to submit patent queries. One
of my colleagues put in a record number of patent queries - about fifty
in one year - and was seen as having rather poor judgement. None of them >>> turned into a patent. He would have benefited from better filtering.
The real evidence is purchase orders.
It seems to be the only evidence you can understand. You seem to have
got your name on exactly one patent, taken out by a group you were
working with, so your grasp of what constitutes a patentable idea and
what you can do with it does seem to be second hand.
On Thu, 2 Apr 2026 14:41:48 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 2/04/2026 3:12 am, john larkin wrote:
On Thu, 2 Apr 2026 02:13:38 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 1/04/2026 7:06 pm, john larkin wrote:
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
<snip>
Invention is precisely running into - running toward - the unexpected. >>>>That's a bizarre way of looking at it. It's doing something in a way
that hasn't been done before, but it is goal directed, and you wouldn't >>>> start the process if you didn't have a pretty clear idea of what you
wanted to do, if not exactly how you were going to do it.
I strongly disagree; that is backwards. Sometimes we imagine products
or circuits that nobody ever wanted or expected. It just happens
sometimes at 2AM.
And very few of them look sensible after the sun has come up.
Most are obviously goofy. Many have already been invented and are on
the market. There are still lots that might become products.
So the next step is to research what's out there. Lately we hire a
bright college student to research the science, technology,
competitors, market. They deliver a report for $1000.
One unstated benefit is that we get to evaluate the kids, even if the technology idea was silly. And it's fun.
I have a folder full of ideas, most speculative and unexpected and
probably dumb.
If you knew a bit more, it would be a much thinner folder.
It would be thicker.
We hire smart kids, college students, to explore them
and write up a report on the possible uses, competitors specs and
pricing, any interesting offshoots that occur to them. They get a
fixed fee when they turn in the report.
An expensive self-indulgence.
Super cheap, compared to the alternates, like hiring a
usually-fatheaded marketing manager.
Sometimes that's accidental, but can be deliberately provoked.None of them useful enough to have been touted at places that encouraged >>>> inventions and applying for patents. EMI Central Research was just such >>>> a place, and I worked there for three years without ever running into
Inventing needs the right skills and personality but improves with
practice in the right environment. Books have been written about that. >>>>
such a book. The histories of Bell Labs
https://en.wikipedia.org/wiki/The_Idea_Factory
I have that one; good book.
Someone said that all the great inventions at Bell in those days were
done by people who ate lunch with Harry Nyquist.
didn't mention any such book either. People will write books with the
flimsiest of justifications if they think the product will sell.
Teaching people how to make genuine inventions would be a very good
thing if you could do it, and a lot of confidence tricksters claim that >>>> they can. The evidence supporting such claims doesn't seem to exist.
The real evidence is purchase orders.
People don't give you purchase orders for patents. They buy products.
Exactly. Patents are "An expensive self-indulgence."
A good and patentable idea can be central to a product, but inept
development can wreck the best of ideas. The Lintech electron beam
tester was based on a patented idea of their boss, whose name was on the
patent (which he'd got to own). He cheap-skated on the development to
such an extent that one of his ex-engineers was able to build a pretty
much identical machine which destroyed his business - nobody ordered a
Lintech machine after the Schlumberger competitor hit the market, and
after Lintech had delivered the last of the machine it had sold they
went bankrupt. Mike Engelhart - of LTSpice fame - worked on that project. >>
Some people invent things. Some intelligent and (over)educated people >>>>> actively resent invention, because they can't do it.
I can't say that I've met any of them. My father and two of my friends >>>> have each got their names onto about 25 patents and none of them ever
talked about people resenting that work.
Given an enormous space of undiscovered ideas, one profits from a >>>>>>> method of exploring them in parallel with minimal filtering.
At EMI Central Research we were encourage to submit patent queries. One >>>> of my colleagues put in a record number of patent queries - about fifty >>>> in one year - and was seen as having rather poor judgement. None of them >>>> turned into a patent. He would have benefited from better filtering.
The real evidence is purchase orders.
It seems to be the only evidence you can understand. You seem to have
got your name on exactly one patent, taken out by a group you were
working with, so your grasp of what constitutes a patentable idea and
what you can do with it does seem to be second hand.
Why the obsession with patents?
Only a small fraction of patents become commercial successes. Most are abandoned in the expensive process before they are issued, and then
most issued patents are abandoned because of the maintenance fees.
Expensive vanity, mostly. OK if you are a big drug company maybe.
On 3/04/2026 1:53 am, john larkin wrote:
On Thu, 2 Apr 2026 14:41:48 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 2/04/2026 3:12 am, john larkin wrote:
On Thu, 2 Apr 2026 02:13:38 +1100, Bill Sloman <bill.sloman@ieee.org><snip>
wrote:
On 1/04/2026 7:06 pm, john larkin wrote:
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote:
On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>> On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>
Invention is precisely running into - running toward - the unexpected. >>>>>That's a bizarre way of looking at it. It's doing something in a way >>>>> that hasn't been done before, but it is goal directed, and you wouldn't >>>>> start the process if you didn't have a pretty clear idea of what you >>>>> wanted to do, if not exactly how you were going to do it.
I strongly disagree; that is backwards. Sometimes we imagine products
or circuits that nobody ever wanted or expected. It just happens
sometimes at 2AM.
And very few of them look sensible after the sun has come up.
Most are obviously goofy. Many have already been invented and are on
the market. There are still lots that might become products.
Not a particularly plausible claim.
So the next step is to research what's out there. Lately we hire a
bright college student to research the science, technology,
competitors, market. They deliver a report for $1000.
Bright college students don't know all that much. They can learn, but
their point of view is shaped by an education system that tells them
what to think, and that does tend to concentrate on area that are easy
to teach.
One unstated benefit is that we get to evaluate the kids, even if the
technology idea was silly. And it's fun.
It will tell you quite a bit about the kids.
I have a folder full of ideas, most speculative and unexpected and
probably dumb.
If you knew a bit more, it would be a much thinner folder.
It would be thicker.
Dream on.
We hire smart kids, college students, to explore them
and write up a report on the possible uses, competitors specs and
pricing, any interesting offshoots that occur to them. They get a
fixed fee when they turn in the report.
An expensive self-indulgence.
Super cheap, compared to the alternates, like hiring a
usually-fatheaded marketing manager.
The usual term is market research organisation. Marketing manager look
after the people who talk to the customers - Tom Peters thought that
that ought to include the engineers but marketing managers don't feel
that they can control what the engineers tell the customers.
Sometimes that's accidental, but can be deliberately provoked.None of them useful enough to have been touted at places that encouraged >>>>> inventions and applying for patents. EMI Central Research was just such >>>>> a place, and I worked there for three years without ever running into >>>>> such a book. The histories of Bell Labs
Inventing needs the right skills and personality but improves with >>>>>> practice in the right environment. Books have been written about that. >>>>>
https://en.wikipedia.org/wiki/The_Idea_Factory
I have that one; good book.
Someone said that all the great inventions at Bell in those days were
done by people who ate lunch with Harry Nyquist.
didn't mention any such book either. People will write books with the >>>>> flimsiest of justifications if they think the product will sell.
Teaching people how to make genuine inventions would be a very good
thing if you could do it, and a lot of confidence tricksters claim that >>>>> they can. The evidence supporting such claims doesn't seem to exist.
The real evidence is purchase orders.
People don't give you purchase orders for patents. They buy products.
Exactly. Patents are "An expensive self-indulgence."
They can be. But they were invented to let people publish and sell their >trade secrets, and it is a system that does make sense if you use it >sensibly.
A good and patentable idea can be central to a product, but inept
development can wreck the best of ideas. The Lintech electron beam
tester was based on a patented idea of their boss, whose name was on the >>> patent (which he'd got to own). He cheap-skated on the development to
such an extent that one of his ex-engineers was able to build a pretty
much identical machine which destroyed his business - nobody ordered a
Lintech machine after the Schlumberger competitor hit the market, and
after Lintech had delivered the last of the machine it had sold they
went bankrupt. Mike Engelhart - of LTSpice fame - worked on that project. >>>
Some people invent things. Some intelligent and (over)educated people >>>>>> actively resent invention, because they can't do it.
I can't say that I've met any of them. My father and two of my friends >>>>> have each got their names onto about 25 patents and none of them ever >>>>> talked about people resenting that work.
Given an enormous space of undiscovered ideas, one profits from a >>>>>>>> method of exploring them in parallel with minimal filtering.
At EMI Central Research we were encourage to submit patent queries. One >>>>> of my colleagues put in a record number of patent queries - about fifty >>>>> in one year - and was seen as having rather poor judgement. None of them >>>>> turned into a patent. He would have benefited from better filtering.
The real evidence is purchase orders.
It seems to be the only evidence you can understand. You seem to have
got your name on exactly one patent, taken out by a group you were
working with, so your grasp of what constitutes a patentable idea and
what you can do with it does seem to be second hand.
Why the obsession with patents?
It's the same idea as scientists exploit when they publish their results
in peer-reviewed journal. You create a free market for good ideas.
Only a small fraction of patents become commercial successes. Most are
abandoned in the expensive process before they are issued, and then
most issued patents are abandoned because of the maintenance fees.
All true. The Lintech patent was taken out by Cambridge Instruments and >abandoned when the parent company went bust. The graduate student half
of the two named inventors took over the patent by paying the
maintenance fees. It was a wise move, and would have paid off even
better if he'd paid more attention the people who ended up using the >machines rather than to the bosses who bought them.
Expensive vanity, mostly. OK if you are a big drug company maybe.
It's like venture capitalism - 19 out of 20 patents weren't worth taking >out, but the twentieth paid for all the rest. EMI, RCA and IBM all
patented everything they could. The big drug companies have the same >business model.
On Fri, 3 Apr 2026 02:21:22 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 3/04/2026 1:53 am, john larkin wrote:
On Thu, 2 Apr 2026 14:41:48 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 2/04/2026 3:12 am, john larkin wrote:
On Thu, 2 Apr 2026 02:13:38 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote:
On 1/04/2026 7:06 pm, john larkin wrote:
On Wed, 1 Apr 2026 15:54:44 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote:
On 1/04/2026 2:14 am, john larkin wrote:
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 8:40 pm, john larkin wrote:
On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 31/03/2026 2:00 am, john larkin wrote:
On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 30/03/2026 2:18 am, john larkin wrote:
On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 29/03/2026 8:38 am, john larkin wrote:
On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 28/03/2026 5:39 am, john larkin wrote: >>>>>>>>>>>>>>>>>>> On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 22/03/2026 1:52 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>> On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
wrote:
On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>>>>>>>>>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
Super cheap, compared to the alternates, like hiring a
usually-fatheaded marketing manager.
The usual term is market research organisation. Marketing manager look
after the people who talk to the customers - Tom Peters thought that
that ought to include the engineers but marketing managers don't feel
that they can control what the engineers tell the customers.
Engineers are the best choice to talk to customers.
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